ES2174994T3 - Sincronizacion de un detector viterbi con realimentacion para etapa demuestreo. - Google Patents

Sincronizacion de un detector viterbi con realimentacion para etapa demuestreo.

Info

Publication number
ES2174994T3
ES2174994T3 ES96107157T ES96107157T ES2174994T3 ES 2174994 T3 ES2174994 T3 ES 2174994T3 ES 96107157 T ES96107157 T ES 96107157T ES 96107157 T ES96107157 T ES 96107157T ES 2174994 T3 ES2174994 T3 ES 2174994T3
Authority
ES
Spain
Prior art keywords
pll
synchronization
feedback
viterbi detector
demonstration stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES96107157T
Other languages
English (en)
Inventor
Jurgen Kaaden
Gerhard Reiner
Dietmar Brauer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Deutsche Thomson Brandt GmbH
Original Assignee
Deutsche Thomson Brandt GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche Thomson Brandt GmbH filed Critical Deutsche Thomson Brandt GmbH
Application granted granted Critical
Publication of ES2174994T3 publication Critical patent/ES2174994T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/0054Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0062Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10009Improvement or modification of read or write signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10009Improvement or modification of read or write signals
    • G11B20/10037A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10009Improvement or modification of read or write signals
    • G11B20/10222Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/10009Improvement or modification of read or write signals
    • G11B20/10305Improvement or modification of read or write signals signal quality assessment
    • G11B20/10398Improvement or modification of read or write signals signal quality assessment jitter, timing deviations or phase and frequency errors
    • G11B20/10425Improvement or modification of read or write signals signal quality assessment jitter, timing deviations or phase and frequency errors by counting out-of-lock events of a PLL
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10Digital recording or reproducing
    • G11B20/18Error detection or correction; Testing, e.g. of drop-outs
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/33Synchronisation based on error coding or decoding
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00Arrangements for synchronising receiver with transmitter
    • H04L7/02Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334Processing of samples having at least three levels, e.g. soft decisions
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B2220/00Record carriers by type
    • G11B2220/20Disc-shaped record carriers
    • G11B2220/25Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
    • G11B2220/2508Magnetic discs
    • G11B2220/2516Hard disks
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B2220/00Record carriers by type
    • G11B2220/20Disc-shaped record carriers
    • G11B2220/25Disc-shaped record carriers characterised in that the disc is based on a specific recording technology
    • G11B2220/2537Optical discs
    • G11B2220/2562DVDs [digital versatile discs]; Digital video discs; MMCDs; HDCDs
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B2220/00Record carriers by type
    • G11B2220/90Tape-like record carriers

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Error Detection And Correction (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

EN SISTEMAS DE MEMORIA DIGITALES, MAGNETICOS Y OPTICOS PARA DATOS DE AUDIO/VIDEO SE UTILIZAN EN EL CAMPO DE REPRODUCCION SISTEMAS PLL (PHASE LOCKED LOOP) PARA RESINCRONIZACION DE INTERVALO A PARTIR DE LOS DATOS. CON ELLO ES DESVENTAJOSO QUE SE INFLUYA EL PUNTO DE EXPLORACION POR EL COMPORTAMIENTO DEL SISTEMA PLL Y DE LA CORRECCION. PARA MEJORAR EL PUNTO DE TIEMPO DE EXPLORACION DEL SISTEMA COMPLETO, SE AMPLIA EL DETECTO VITERBI PRESENTE EN EL SISTEMA ALREDEDOR DE UNA SALIDA DE CONTROL, DONDE SE CONTROLA UNA CONDUCCION DE RETARDO VARIABLE EN LA SALIDA O DENTRO DEL SISTEMA PLL.
ES96107157T 1995-05-16 1996-05-07 Sincronizacion de un detector viterbi con realimentacion para etapa demuestreo. Expired - Lifetime ES2174994T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19517405A DE19517405A1 (de) 1995-05-16 1995-05-16 Signalverarbeitungssystem für digitale Signale

Publications (1)

Publication Number Publication Date
ES2174994T3 true ES2174994T3 (es) 2002-11-16

Family

ID=7761718

Family Applications (1)

Application Number Title Priority Date Filing Date
ES96107157T Expired - Lifetime ES2174994T3 (es) 1995-05-16 1996-05-07 Sincronizacion de un detector viterbi con realimentacion para etapa demuestreo.

Country Status (6)

Country Link
US (1) US5940449A (es)
EP (1) EP0744848B1 (es)
JP (1) JPH08315518A (es)
DE (2) DE19517405A1 (es)
ES (1) ES2174994T3 (es)
MY (1) MY113906A (es)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19717643C2 (de) 1997-04-25 1999-02-25 Siemens Ag Verfahren und Anordnung zur Regelung der Entscheiderschwelle und des Abtastzeitpunktes eines Datenregenerators
KR100289714B1 (ko) 1997-08-21 2001-05-15 윤종용 데이터검출기및그방법
KR100289821B1 (ko) * 1997-08-21 2001-05-15 윤종용 데이터검출기및그방법
DE19738362B4 (de) 1997-09-02 2006-11-02 Siemens Ag Schaltungsanordnung und Verfahren zur Minimierung von Bitfehlern
US6463109B1 (en) * 1998-08-25 2002-10-08 Vitesse Semiconductor Corporation Multiple channel adaptive data recovery system
US7224759B2 (en) * 2002-07-11 2007-05-29 Honeywell International Inc. Methods and apparatus for delay free phase shifting in correcting PLL phase offset
US7831855B2 (en) * 2007-04-12 2010-11-09 Harris Corporation System and method for generating a reset signal for synchronization of a signal
EP2031791A1 (en) * 2007-08-30 2009-03-04 Deutsche Thomson OHG Apparatus and method for recovering data from a clocked input signal

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3872432A (en) * 1974-04-10 1975-03-18 Itt Synchronization circuit for a viterbi decoder
FR2505059A1 (fr) * 1981-04-30 1982-11-05 Jaeger Electrolyte a support organique, pour cellule d'affichage electrolytique
GB8327084D0 (en) * 1983-10-11 1983-11-09 Gordon J Error correction decoder apparatus
JPS6121660A (ja) * 1984-07-10 1986-01-30 Toshiba Corp 搬送波再生回路
SE462942B (sv) * 1989-01-26 1990-09-17 Ericsson Telefon Ab L M Saett och anordning foer snabb frekvensstyrning av en koherent radiomottagare
JPH03166839A (ja) * 1989-11-27 1991-07-18 Matsushita Electric Ind Co Ltd ディジタル情報検出装置
US5432820A (en) * 1990-11-19 1995-07-11 Fujitsu Limited Maximum-likelihood decoding method and device
DE4102800A1 (de) * 1991-01-31 1992-08-06 Thomson Brandt Gmbh Phasenregelkreis mit nachlaufsynchronisation
JP2702303B2 (ja) * 1991-03-20 1998-01-21 日本電気株式会社 データ通信方式
JP3259302B2 (ja) * 1992-01-28 2002-02-25 株式会社日立製作所 出力信号復号方法および装置
DE4308000B4 (de) * 1993-03-13 2006-11-30 Robert Bosch Gmbh Verfahren zur entscheidungsrückgekoppelten Taktableitung
EP0644661B1 (en) * 1993-09-20 2000-06-14 Canon Kabushiki Kaisha Signal processing apparatus
JPH07111042A (ja) * 1993-10-08 1995-04-25 Hitachi Ltd データ弁別回路
US5550870A (en) * 1994-03-02 1996-08-27 Lucent Technologies Inc. Viterbi processor
JP3015832B2 (ja) * 1995-06-27 2000-03-06 富士通株式会社 データ再生装置
JPH09214294A (ja) * 1996-02-08 1997-08-15 Fujitsu Ltd 自動周波数制御回路

Also Published As

Publication number Publication date
MY113906A (en) 2002-06-29
EP0744848A1 (de) 1996-11-27
JPH08315518A (ja) 1996-11-29
DE19517405A1 (de) 1996-11-21
EP0744848B1 (de) 2002-04-03
DE59608987D1 (de) 2002-05-08
US5940449A (en) 1999-08-17

Similar Documents

Publication Publication Date Title
US7474136B2 (en) Use of multiple voltage controlled delay lines for precise alignment and duty cycle control of the data output of a DDR memory device
ES2165841T3 (es) Sistema de sincronizacion de campo que mantiene la integridad de entrelazado.
ES2174994T3 (es) Sincronizacion de un detector viterbi con realimentacion para etapa demuestreo.
EP0967724A3 (en) Calibrated delay locked loop for DDR SDRAM applications
KR20010070947A (ko) 광 통신 및 네트워킹 시스템에서의 비트 동기화 방법 및장치
SE0001029D0 (sv) Phase-locked loop based clock phasing implementing a virtual delay
Wild Observation of the magnetic structure of a type IV solar radio outburst
CA3058643C (en) Methods and systems with downhole synchronization based on a direct digital synthesizer (dds)
DE60219930D1 (de) Digitaler breitband-phasenregelkreis (pll) mit halbfrequenzausgang
EP1047195A2 (en) Delay locked loop and clock circuit using a delay locked loop
JPH02271794A (ja) クロック信号再発生回路網
US9030907B2 (en) Semiconductor device and semiconductor system with the same
WO2002097990A3 (en) Ultra low jitter clock generation device and method for storage device
TW200606867A (en) Phase locked loop for controlling an optical recording device and method thereof
FI940337A0 (fi) Kellosignaaligeneraattori digitaalista televisiovastaanotinta varten
ATE32966T1 (de) Verriegelte zeitbasis.
ATE191109T1 (de) Integrierbare taktgewinnungsschaltung
IT1311463B1 (it) Metodo di recupero del segnale d'orologio in un sistema ditelecomunicazioni e relativo circuito.
KR20090089305A (ko) 멀티미디어 시스템에서의 최소개의 크리스탈들을 이용한 클록 발생기
SE9301327L (sv) Referenssignal sammansatt av klocksignal och synkroniseringssignal, anordning och förfarande för synkronisering m.h.a. referenssignal
SE9600726L (sv) Digital faslåst slinga
ATE410852T1 (de) Datenverarbeitungsvorrichtung mit taktrückgewinnung aus unterschiedlichen quellen
FI894154A0 (fi) Skenbart linjelaost skrivklocka foer bild-i-bild-videotillaempningar.
KR20030014790A (ko) 지연 동기 루프
JPS5910048A (ja) スペクトラム拡散通信装置の同期方式

Legal Events

Date Code Title Description
FG2A Definitive protection

Ref document number: 744848

Country of ref document: ES