ES2183600T3 - Procedimiento para la conexion de chips de conexion. - Google Patents

Procedimiento para la conexion de chips de conexion.

Info

Publication number
ES2183600T3
ES2183600T3 ES99944118T ES99944118T ES2183600T3 ES 2183600 T3 ES2183600 T3 ES 2183600T3 ES 99944118 T ES99944118 T ES 99944118T ES 99944118 T ES99944118 T ES 99944118T ES 2183600 T3 ES2183600 T3 ES 2183600T3
Authority
ES
Spain
Prior art keywords
connection
carrier substrate
procedure
chip
connection chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES99944118T
Other languages
English (en)
Inventor
Michael Feil
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung eV
Original Assignee
Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung eV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19845296A external-priority patent/DE19845296A1/de
Application filed by Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung eV filed Critical Fraunhofer-Gesellschaft zur Förderung der Angewandten Forschung eV
Application granted granted Critical
Publication of ES2183600T3 publication Critical patent/ES2183600T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
    • G06K19/07752—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna using an interposer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/141—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being on at least the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Wire Bonding (AREA)

Abstract

Procedimiento para la conexión de un chip de conexión (2) de un grosor inferior a 50 m que contiene una conexión integrada, que presenta al menos dos superficies de conexión (8, 10) en su parte superior, con los siguientes pasos: Introducir el chip de conexión (2) con su parte inferior sobre una superficie de un sustrato portador (4), de tal manera que el chip de conexión (2) sobresalga con su grosor total de la superficie del sustrato portador (4); y Aplicar un recubrimiento metálico (16) estructurado mediante un proceso de estampación o de sellado sobre la parte superior del chip de conexión (2) y sobre la superficie del sustrato portador (4) para fabricar una estructura conductora (16) periférica que está unida con las superficies de conexión del chip de conexión (2) sobre la superficie del sustrato portador (4) y la parte superior del chip de conexión (2).
ES99944118T 1998-09-03 1999-08-27 Procedimiento para la conexion de chips de conexion. Expired - Lifetime ES2183600T3 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19840193 1998-09-03
DE19845296A DE19845296A1 (de) 1998-09-03 1998-10-01 Verfahren zur Kontaktierung eines Schaltungschips

Publications (1)

Publication Number Publication Date
ES2183600T3 true ES2183600T3 (es) 2003-03-16

Family

ID=26048597

Family Applications (1)

Application Number Title Priority Date Filing Date
ES99944118T Expired - Lifetime ES2183600T3 (es) 1998-09-03 1999-08-27 Procedimiento para la conexion de chips de conexion.

Country Status (4)

Country Link
US (1) US6365440B1 (es)
EP (1) EP1116180B1 (es)
ES (1) ES2183600T3 (es)
WO (1) WO2000014679A1 (es)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7009576B2 (en) * 2002-06-11 2006-03-07 Michelin Recherche Et Technique S.A. Radio frequency antenna for a tire and method for same
JP2005311118A (ja) * 2004-04-22 2005-11-04 Seiko Epson Corp 半導体装置及びその製造方法、電気光学装置、並びに電子機器
JP2006303408A (ja) * 2004-09-09 2006-11-02 Seiko Epson Corp 電子装置及びその製造方法
JP2006270009A (ja) * 2005-02-25 2006-10-05 Seiko Epson Corp 電子装置の製造方法
GB2436164A (en) * 2006-03-16 2007-09-19 Uvasol Ltd Improvements in electrical connections between electronic components and conductive tracks
DE102010062547B4 (de) * 2010-12-07 2021-10-28 Semikron Elektronik Gmbh & Co. Kg Verfahren zur Herstellung einer Schaltungsanordnung

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DD134471A1 (de) 1977-12-12 1979-02-28 Uwe Loreit Verfahren zur kontaktierung von halbleiterchips mit traegerkoerpern
US5155068A (en) 1989-08-31 1992-10-13 Sharp Kabushiki Kaisha Method for manufacturing an IC module for an IC card whereby an IC device and surrounding encapsulant are thinned by material removal
DE4207874C2 (de) 1992-03-12 2002-12-12 Fraunhofer Ges Forschung Visuelle Kontrolleinrichtung
DE4304422C1 (de) 1993-02-13 1994-07-21 Winter & Ibe Olympus Endoskop
DE4431606A1 (de) * 1994-09-05 1996-03-07 Siemens Ag Chipkartenmodul für eine kontaktlose Chipkarte und Verfahren zu deren Herstellung
DE4432254A1 (de) 1994-09-10 1996-03-14 Didier Werke Ag Verfahren zum Anpressen eines Ausflußorgans an ein metallurgisches Gefäß
DE4433845A1 (de) 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung
EP0772153A3 (en) * 1995-10-31 1999-06-23 Lucent Technologies Inc. Smart card having a thin die
DE19642378C2 (de) 1996-10-14 2000-06-08 Fraunhofer Ges Forschung Kontaktlose Chipkarte
FR2761497B1 (fr) * 1997-03-27 1999-06-18 Gemplus Card Int Procede de fabrication d'une carte a puce ou analogue
DE19713799A1 (de) 1997-04-03 1998-10-08 Plettner Andreas Datenrecorder
DE29813738U1 (de) 1997-09-09 1999-03-04 Haberger Karl Vorrichtung zum manipulationssicheren Kennzeichnen von Gegenständen

Also Published As

Publication number Publication date
US6365440B1 (en) 2002-04-02
EP1116180A1 (de) 2001-07-18
EP1116180B1 (de) 2002-10-02
WO2000014679A1 (de) 2000-03-16

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