ES2192863T3 - Procedimiento de procesamiento de un sistema electronico sometido a limitaciones por errores transitorios. - Google Patents

Procedimiento de procesamiento de un sistema electronico sometido a limitaciones por errores transitorios.

Info

Publication number
ES2192863T3
ES2192863T3 ES99947525T ES99947525T ES2192863T3 ES 2192863 T3 ES2192863 T3 ES 2192863T3 ES 99947525 T ES99947525 T ES 99947525T ES 99947525 T ES99947525 T ES 99947525T ES 2192863 T3 ES2192863 T3 ES 2192863T3
Authority
ES
Spain
Prior art keywords
processing
cycle
electronic system
limitations
context
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES99947525T
Other languages
English (en)
Inventor
Michel Pignol
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centre National dEtudes Spatiales CNES
Original Assignee
Centre National dEtudes Spatiales CNES
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Centre National dEtudes Spatiales CNES filed Critical Centre National dEtudes Spatiales CNES
Application granted granted Critical
Publication of ES2192863T3 publication Critical patent/ES2192863T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operations
    • G06F11/1497—Time redundant execution of software on a single processing unit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operations
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1438—Restarting or rejuvenating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1466—Key-lock mechanism

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Security & Cryptography (AREA)
  • Hardware Redundancy (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Storage Device Security (AREA)
  • Debugging And Monitoring (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Retry When Errors Occur (AREA)

Abstract

Procedimiento de procesamiento de un sistema electrónico sometido a limitaciones por errores transitorios, caracterizado porque, en un ciclo en tiempo real determinado, es decir, en un ciclo de funcionamiento determinado de una tarea lógica que se ejecuta de forma periódica y continua, se multiplexan en el tiempo dos cadenas virtuales insertadas en una única cadena física; almacenándose los datos resultantes de cada ejecución de una cadena virtual para ser votados antes de su uso, y por que, en caso de detección de errores, se invalida el ciclo real en curso, y se carga un contexto en buen estado para efectuar una reanudación, que consiste en una ejecución nominal del ciclo siguiente a partir del contexto cargado.
ES99947525T 1998-10-12 1999-10-11 Procedimiento de procesamiento de un sistema electronico sometido a limitaciones por errores transitorios. Expired - Lifetime ES2192863T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9812745A FR2784475B1 (fr) 1998-10-12 1998-10-12 Procede de traitement d'un systeme electronique soumis a des contraintes d'erreurs transitoires

Publications (1)

Publication Number Publication Date
ES2192863T3 true ES2192863T3 (es) 2003-10-16

Family

ID=9531439

Family Applications (1)

Application Number Title Priority Date Filing Date
ES99947525T Expired - Lifetime ES2192863T3 (es) 1998-10-12 1999-10-11 Procedimiento de procesamiento de un sistema electronico sometido a limitaciones por errores transitorios.

Country Status (7)

Country Link
US (1) US6839868B1 (es)
EP (2) EP1267265A3 (es)
JP (2) JP4671507B2 (es)
DE (1) DE69905272T2 (es)
ES (1) ES2192863T3 (es)
FR (1) FR2784475B1 (es)
WO (1) WO2000022529A1 (es)

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US20040019895A1 (en) * 2002-07-29 2004-01-29 Intel Corporation Dynamic communication tuning apparatus, systems, and methods
US20050193283A1 (en) * 2003-12-30 2005-09-01 Reinhardt Steven K. Buffering unchecked stores for fault detection in redundant multithreading systems using speculative memory support
US7328377B1 (en) 2004-01-27 2008-02-05 Altera Corporation Error correction for programmable logic integrated circuits
DE102004019371B4 (de) * 2004-04-21 2006-04-13 Siemens Ag Verfahren zur Wiederherstellung eines Betriebszustands eines Systems
US7166847B2 (en) * 2004-06-30 2007-01-23 Intel Corporation System with response to cosmic ray detection
DE102004037713A1 (de) * 2004-08-04 2006-03-16 Robert Bosch Gmbh Verfahren, Betriebssystem und Rechengerät zum Abarbeiten eines Computerprogramms
DE102004051966A1 (de) 2004-10-25 2006-05-04 Robert Bosch Gmbh Verfahren, Betriebssystem und Rechengerät zum Abarbeiten eines Computerprogramms
DE102005023296B4 (de) * 2005-05-12 2007-07-12 Siemens Ag Zugbeeinflussungssystem
US7272681B2 (en) * 2005-08-05 2007-09-18 Raytheon Company System having parallel data processors which generate redundant effector date to detect errors
JP2007133807A (ja) * 2005-11-14 2007-05-31 Hitachi Ltd データ処理システム、ストレージ装置及び管理装置
US8024639B2 (en) 2006-06-23 2011-09-20 Schweitzer Engineering Laboratories, Inc. Software and methods to detect and correct data structure
US20080080114A1 (en) * 2006-09-29 2008-04-03 Schweitzer Engineering Laboratories, Inc. Apparatus, systems and methods for reliably detecting faults within a power distribution system
US7702971B2 (en) * 2007-06-06 2010-04-20 Dell Products L.P. System and method for predictive failure detection
US20110099439A1 (en) * 2009-10-23 2011-04-28 Infineon Technologies Ag Automatic diverse software generation for use in high integrity systems
US20110208948A1 (en) * 2010-02-23 2011-08-25 Infineon Technologies Ag Reading to and writing from peripherals with temporally separated redundant processor execution
US8516356B2 (en) 2010-07-20 2013-08-20 Infineon Technologies Ag Real-time error detection by inverse processing
US8441768B2 (en) 2010-09-08 2013-05-14 Schweitzer Engineering Laboratories Inc Systems and methods for independent self-monitoring
US9007731B2 (en) 2012-03-26 2015-04-14 Schweitzer Engineering Laboratories, Inc. Leveraging inherent redundancy in a multifunction IED
US8955157B2 (en) * 2012-07-03 2015-02-10 Honeywell International Inc. Method and apparatus for differential power analysis protection
US9270792B2 (en) * 2012-11-21 2016-02-23 Ubiquiti Networks, Inc. Method and system for improving wireless link efficiency
EP3279796B1 (en) * 2016-08-02 2020-07-15 NXP USA, Inc. Resource access management component and method therefor
IT201800007412A1 (it) * 2018-07-23 2020-01-23 Sistema elettronico modulare per la verifica della corretta esecuzione di operazioni eseguite dal sistema stesso
US11323362B2 (en) 2020-08-07 2022-05-03 Schweitzer Engineering Laboratories, Inc. Resilience to single event upsets in software defined networks

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Also Published As

Publication number Publication date
JP5283650B2 (ja) 2013-09-04
DE69905272D1 (de) 2003-03-13
EP1267265A3 (fr) 2005-08-17
DE69905272T2 (de) 2003-12-11
US6839868B1 (en) 2005-01-04
FR2784475B1 (fr) 2000-12-29
JP2010134967A (ja) 2010-06-17
EP1121642A1 (fr) 2001-08-08
EP1267265A2 (fr) 2002-12-18
WO2000022529A1 (fr) 2000-04-20
EP1121642B1 (fr) 2003-02-05
JP4671507B2 (ja) 2011-04-20
FR2784475A1 (fr) 2000-04-14
JP2002527820A (ja) 2002-08-27

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