ES2194780T3 - Circuito integrado con al menos dos sistemas de pulsos de reloj. - Google Patents

Circuito integrado con al menos dos sistemas de pulsos de reloj.

Info

Publication number
ES2194780T3
ES2194780T3 ES00967591T ES00967591T ES2194780T3 ES 2194780 T3 ES2194780 T3 ES 2194780T3 ES 00967591 T ES00967591 T ES 00967591T ES 00967591 T ES00967591 T ES 00967591T ES 2194780 T3 ES2194780 T3 ES 2194780T3
Authority
ES
Spain
Prior art keywords
clock pulse
tree
integrated circuit
input
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES00967591T
Other languages
English (en)
Inventor
Majid Ghameshlu
Karlheinz Krause
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Application granted granted Critical
Publication of ES2194780T3 publication Critical patent/ES2194780T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

Circuito integrado con al menos dos sistemas de pulsos de reloj, en los que el pulso de reloj correspondiente puede ser transmitido, a partir de una entrada de pulso de reloj (TE1, TE2), a través de árboles de pulsos de reloj (CT1, CT2, CT3), hacia elementos o bloques de conmutación (FFi) individuales, así como con al menos un conmutador (MU1, MU2, MU3) controlado, con cuya ayuda se puede aplicar, para estados de funcionamiento seleccionados, un único pulso de reloj común para todos los árboles de pulsos de reloj, estando conectada una unidad PLL (PL1) al menos aguas arriba de un primer árbol de pulsos de reloj (CT1, CT2) y estando conectada una salida de este árbol de pulsos de reloj con una entrada de la unidad PLL, para la formación de un bucle de regulación de las fases (PLL), caracterizado porque a cada árbol de pulsos de reloj (CT1, CT2, CT3) está asociado un conmutador (MU1, MU2, MU3) controlado y los conmutadores están activados en los estados de funcionamiento seleccionados de talforma que el pulso de reloj común es alimentado solamente a un último árbol de pulsos de reloj (CT3) y una salida de este árbol de pulsos de reloj está conectada con la otra entrada de la unidad PLL al menos del primer árbol de pulsos de reloj (CT1, CT2).
ES00967591T 1999-09-22 2000-09-19 Circuito integrado con al menos dos sistemas de pulsos de reloj. Expired - Lifetime ES2194780T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19945421 1999-09-22

Publications (1)

Publication Number Publication Date
ES2194780T3 true ES2194780T3 (es) 2003-12-01

Family

ID=7922910

Family Applications (1)

Application Number Title Priority Date Filing Date
ES00967591T Expired - Lifetime ES2194780T3 (es) 1999-09-22 2000-09-19 Circuito integrado con al menos dos sistemas de pulsos de reloj.

Country Status (6)

Country Link
US (1) US6639442B1 (es)
EP (1) EP1214788B1 (es)
CN (1) CN1214529C (es)
DE (1) DE50001580D1 (es)
ES (1) ES2194780T3 (es)
WO (1) WO2001022588A1 (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW578388B (en) * 2002-12-19 2004-03-01 Prolific Technology Inc Clock generating circuit and method thereof
US6847241B1 (en) * 2003-07-25 2005-01-25 Xilinx, Inc. Delay lock loop using shift register with token bit to select adjacent clock signals
FR2866435B1 (fr) * 2004-02-13 2008-04-04 Inst Nat Polytech Grenoble Procede d'elaboration automatique de fichiers de description hdl de systeme electronique digital integre et systeme digital elecronique integre obtenu
DE102004062210B3 (de) 2004-12-23 2006-05-24 Texas Instruments Deutschland Gmbh Dualmodultaktversorgung für CAN-Kommunikationsmodul
JP4641215B2 (ja) * 2005-05-20 2011-03-02 株式会社日立製作所 負荷駆動回路、集積回路、及びプラズマディスプレイ
US7486130B2 (en) * 2005-12-14 2009-02-03 Ember Corporation Clock skew compensation
CN101216722B (zh) * 2008-01-08 2010-08-11 北京中星微电子有限公司 一种时钟管理方法及装置
US8526559B2 (en) * 2008-05-30 2013-09-03 Mediatek Inc. Communication systems and clock generation circuits thereof with reference source switching
CN103033739A (zh) * 2012-12-20 2013-04-10 天津联芯科技有限公司 可程控的纳米级别集成电路内置自检控制器
CN103677077A (zh) * 2013-12-18 2014-03-26 西安智多晶微电子有限公司 强化时钟管理的复杂可编程逻辑器件
CN107340800B (zh) * 2015-01-23 2019-06-14 西安智多晶微电子有限公司 带有延迟反馈回路的cpld

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63238714A (ja) * 1986-11-26 1988-10-04 Hitachi Ltd クロック供給システム
US5329188A (en) 1991-12-09 1994-07-12 Cray Research, Inc. Clock pulse measuring and deskewing system and process
JP2771464B2 (ja) 1994-09-29 1998-07-02 日本電気アイシーマイコンシステム株式会社 ディジタルｐｌｌ回路
US5517147A (en) * 1994-11-17 1996-05-14 Unisys Corporation Multiple-phase clock signal generator for integrated circuits, comprising PLL, counter, and logic circuits
US5578945A (en) * 1994-11-30 1996-11-26 Unisys Corporation Methods and apparatus for providing a negative delay on an IC chip
US6100734A (en) * 1994-11-30 2000-08-08 Unisys Corporation IC chip using a phase-locked loop for providing signals having different timing edges
US5870445A (en) * 1995-12-27 1999-02-09 Raytheon Company Frequency independent clock synchronizer
US5944834A (en) 1997-09-26 1999-08-31 International Business Machines Corporation Timing analysis method for PLLS
US6114877A (en) * 1998-06-03 2000-09-05 Agilent Technologies, Inc. Timing circuit utilizing a clock tree as a delay device

Also Published As

Publication number Publication date
WO2001022588A1 (de) 2001-03-29
CN1214529C (zh) 2005-08-10
EP1214788A1 (de) 2002-06-19
US6639442B1 (en) 2003-10-28
CN1402907A (zh) 2003-03-12
EP1214788B1 (de) 2003-03-26
DE50001580D1 (de) 2003-04-30

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