ES2301802T3 - COMPLETELY DIGITAL GAIN CONTROL METHOD AND SYSTEM. - Google Patents
COMPLETELY DIGITAL GAIN CONTROL METHOD AND SYSTEM. Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/40—Monitoring; Testing of relay systems
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G7/00—Volume compression or expansion in amplifiers
- H03G7/06—Volume compression or expansion in amplifiers having semiconductor devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/001—Digital control of analog signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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- H03M1/1235—Non-linear conversion not otherwise provided for in subgroups of H03M1/12
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Abstract
Description
Método y sistema de control de ganancia completamente digital.Method and gain control system completely digital.
La invención presente trata del campo de las comunicaciones inalámbricas. Más específicamente, la invención presente trata de una arquitectura de control de ganancia completamente digital.The present invention deals with the field of wireless communications More specifically, the invention present is about a gain control architecture completely digital.
En la mayoría de los sistemas de comunicaciones inalámbricos, la señal de banda base en el receptor se convierte del formato analógico al formato digital de manera que se pueda recuperar la información útil a través de una secuencia de proceso digital. El dispositivo común que consigue esta conversión es un convertidor analógico-a-digital (ADC). Una de las especificaciones más importantes de un convertidor analógico digital es el número de bits de salida. En general, cuantos más bits de salida tiene el convertidor analógico digital, más grande es el rango dinámico de la señal de entrada que el convertidor analógico digital puede soportar. Sin embargo, esto tiene el resultado de un convertidor analógico digital más caro, al igual que el resto de los componentes del receptor. Dado un número de bits de salida, si la potencia de la señal de entrada es demasiado alta, la salida del convertidor analógico digital puede resultar saturada. Por el contrario, si la potencia de la señal de entrada es demasiado pequeña, la señal de salida puede resultar seriamente incompleta. En ambos casos, la información que debe ser recuperada en el receptor puede resultar perdida. Una manera común de resolver este problema es aplicar un amplificador de ganancia ajustable dinámicamente antes del convertidor analógico digital de manera que la señal de entrada al convertidor analógico digital puede ser mantenida al nivel deseado. Típicamente, la ganancia ajustable se controla utilizando un mecanismo de bucle, como se muestra en la Figura 1, al que se denomina también control automático de ganancia (AGC).In most communications systems wireless, the baseband signal in the receiver is converted from analog to digital format so that you can retrieve useful information through a process sequence digital. The common device that achieves this conversion is a analog-to-digital converter (ADC). One of the most important specifications of a Digital analog converter is the number of output bits. In In general, the more output bits the analog converter has digital, larger is the dynamic range of the input signal that The digital analog converter can support. However, this it has the result of a more expensive digital analog converter, at same as the rest of the receiver components. Given a number of output bits, if the power of the input signal is too high, the digital analog converter output may be saturated On the contrary, if the signal strength of input is too small, the output signal may result seriously incomplete In both cases, the information that must be recovered in the receiver may be lost. A common way to solve this problem is to apply a gain amplifier dynamically adjustable before the digital analog converter way that the input signal to the digital analog converter It can be maintained at the desired level. Typically, the gain Adjustable is controlled using a loop mechanism, as shown in Figure 1, which is also called control Automatic gain (AGC).
La solicitud de Patente japonesa que tiene el número de publicación 2000236276 describe un receptor digital de banda ancha que comprende un amplificador logarítmico seguido de un amplificador de control automático de ganancia y de un convertidor analógico digital, siendo la salida de dicho convertidor analógico digital retroalimentada al amplificador para ajustar dinámicamente su ganancia. Además, el receptor comprende un circuito de expansión exponencial para expandir la señal digital comprimida suministrada por el amplificador logarítmico y el convertidor analógico digital.The Japanese patent application that has the Publication number 2000236276 describes a digital receiver of broadband comprising a logarithmic amplifier followed by a Automatic gain control amplifier and converter digital analog, the output of said analog converter being digital feedback to the amplifier to dynamically adjust Your profit In addition, the receiver comprises an expansion circuit exponential to expand the compressed digital signal supplied by the logarithmic amplifier and the analog converter digital.
En la práctica, se deben considerar diversos requisitos cuando se utilizan controles automáticos de ganancia. Los controladores automáticos de ganancia deben ser lo bastante rápidos para compensar las variaciones de potencia del canal, pero deben ser lo bastante lentos como para no distorsionar la señal contenida. Los controles automáticos de ganancia no deben alterar la fase de inserción a la radio (de manera que no se sobrecargue el bucle de desrotación). Los controles automáticos de ganancia deben tener también una respuesta lineal (en decibelios por voltio). Los controles automáticos de ganancia son sistemas de control de bucle cerrado, de manera que tienen estabilidad, responden a los requisitos de constante de tiempo y sobremuestreo así como a otras cuestiones de diseño que deben ser consideradas. Se requiere de un control automático de ganancia que tenga líneas de control desde el módem, y a menudo un convertidor digital a analógico adicional (DAC). En los modos de división de tiempo dúplex (TDD) y en la división de tiempo de acceso múltiple (TDMA), el control automático de ganancia debe reajustar la ganancia de la radio muy rápido ante la ocurrencia de un salto desconocido muy grande en la potencia de entrada. El control automático de ganancia requiere una arquitectura de radio específica con control de ganancia, suponiendo ambas características mayores coste y consumo de energía. El control automático de ganancia tiene también desventajas de diseño entre NF e IP3, en especial en presencia de una gran perturbación. IP3 es un punto de intercepción de tercer orden. NF es una figura de ruido. Cuanto mayor es la ganancia antes del convertidor (demodulador) mejor (más baja) resulta la NF, pero también disminuye la IP3 (lo que no es bueno). En la práctica, algunos de los requisitos explicados resultan difíciles de conseguir. Se deben asumir ciertos compromisos, que resultan en un cierto grado de pérdida en el nivel de prestaciones del sistema.In practice, several must be considered requirements when automatic gain controls are used. Automatic gain controllers must be enough fast to compensate for channel power variations, but they must be slow enough not to distort the signal contained. Automatic gain controls should not alter the radio insertion phase (so that the rotation loop). Automatic gain controls must also have a linear response (in decibels per volt). The Automatic gain controls are loop control systems closed, so that they have stability, respond to time and oversampling requirements as well as others Design issues that should be considered. It requires a automatic gain control that has control lines from the modem, and often an additional digital to analog converter (DAC). In duplex time division (TDD) modes and in the Multiple access time division (TDMA), automatic control gain must readjust the radio gain very fast before the occurrence of a very large unknown leap in the power of entry. Automatic gain control requires an architecture specific radio with gain control, assuming both Features higher cost and energy consumption. The control Automatic gain also has design disadvantages between NF and IP3, especially in the presence of a great disturbance. IP3 is a third order intercept point. NF is a noise figure. The higher the gain before the converter (demodulator) better (lower) is the NF, but also decreases the IP3 (what that's not good). In practice, some of the requirements explained are difficult to achieve. Certain must be assumed commitments, which result in a certain degree of loss at the level of system benefits.
La Patente de los estados Unidos número 4,124,773 describe un sistema de comunicaciones de audio para transmitir señales analógicas a través de las líneas de comunicaciones. El sistema recibe una señal analógica que se comprime mediante un compresor antes de ser convertida en una señal digital por un convertidor analógico digital. La señal digital comprimida se transmite a continuación a través de una línea de comunicación. En un lugar de recepción remoto, un convertidor digital analógico (DAC) convierte la señal digital en su representación analógica comprimida. Tras la recuperación de la señal analógica comprimida mediante el convertidor digital analógico, un expansor reconstruye la forma de la onda analógica original.United States Patent Number 4,124,773 describes an audio communications system for transmit analog signals through the lines of communications The system receives an analog signal that is compressed by a compressor before being converted into a signal digital by a digital analog converter. The digital signal compressed is then transmitted through a line of communication. In a remote reception location, a converter analog digital (DAC) converts the digital signal into your compressed analog representation. After the recovery of the analog signal compressed by digital converter analog, an expander reconstructs the shape of the analog wave original.
La Patente de los Estados Unidos número 4,903,020 describe un amplificador para amplificar una señal analógica comprimida y transmitir la señal comprimida a un convertidor analógico digital para convertirla en una señal digital comprimida. La salida del convertidor analógico digital se conecta a un expansor digital desde el que se transmiten las señales digitales expandidas, por ejemplo a un proceso digital adicional, transmisión o conversión digital a analógica.United States Patent Number 4,903,020 describes an amplifier to amplify a signal compressed analog and transmit the compressed signal to a digital analog converter to convert it into a digital signal compressed The output of the digital analog converter is connected to a digital expander from which signals are transmitted expanded digital, for example to an additional digital process, digital to analog transmission or conversion.
La Patente de los Estados Unidos número 5,446,761 describe un circuito decodificador y un método para proporcionar una señal compensada en amplitud mediante el filtrado del efecto indeseable de la modulación de amplitud en una señal de fase modulada. El método de decodificación consiste en el desmodulado del componente de la señal recibida en la fase de recepción y hacer la cuadratura de la componente de la señal de recepción de la señal modulada en fase y extraer una señal que varía en amplitud e introducirla en un circuito de control de ganancia automático del que sale la señal compensada en amplitud. El circuito de alimentación con control automático de ganancia comprende un circuito detector, un circuito de compensación de la polarización, un circuito diferenciador y un circuito de control de ganancia. El circuito detector proporciona una salida que es una señal de corriente continua que representa la amplitud de la señal recibida en fase y de la señal recibida en cuadratura. El circuito de compensación de la polarización proporciona una polarización constante de la corriente a la señal de corriente continua creando así una señal de control. El circuito de control de ganancia recibe la señal de control y la señal de amplitud variable y proporciona una salida que es una señal de amplitud compensada.United States Patent Number 5,446,761 describes a decoder circuit and a method for provide an amplitude compensated signal by filtering of the undesirable effect of amplitude modulation on a signal of modulated phase The decoding method consists of demodulated component of the signal received in the phase of reception and square the signal component of reception of the phase modulated signal and extract a signal that varies in amplitude and introduce it into a control circuit of automatic gain from which the compensated signal in amplitude comes out. The power circuit with automatic gain control it comprises a detector circuit, a compensation circuit of the polarization, a differentiating circuit and a control circuit of gain. The detector circuit provides an output that is a DC signal representing the amplitude of the signal received in phase and the signal received in quadrature. The circuit polarization compensation provides polarization constant of the current to the direct current signal creating So a control signal. The gain control circuit receives the control signal and the variable amplitude signal and provides an output that is a signal of compensated amplitude.
La Patente de los Estados Unidos número 5,572,542 describe un dispositivo y un método para conseguir una precisión de ganancia internamente a partir de un procesador de señal digital convencional generando una señal de control de ganancia automático (AGC). El bit de la señal de salida del control de ganancia automático es indicativo de la salida del procesador de señal digital siendo multiplicada por un factor de ganancia cuando la salida del filtro digital incluido en el procesador de señal digital está por debajo de un valor de consigna. Cuando la señal de salida del control de ganancia automático se recibe mediante una fase de entrada y un convertidor de cuadratura (I/Q)-a-(logR/phi) conectado al procesador de señal digital, se sustrae un valor correspondiente del componente de radio de la señal calculado por el convertidor (I/Q)-a-(logR/phi). Debido a que el procesador de señal digital convencional tiene 16 bits de entrada/salida, la señal de salida del control automático de ganancia permite una señal entrada con un rango dinámico y una precisión que excede los 16 bits para ser transferida desde el procesador de señal digital sin pérdida de rendimiento. Como resultado, se puede implementar un procesador de señal digital con un número de bits de entrada/salida menor del requerido normalmente para la precisión y el rango dinámico de la señal de salida.United States Patent Number 5,572,542 describes a device and a method to achieve a gain accuracy internally from a processor conventional digital signal generating a control signal of automatic gain (AGC). The bit of the control output signal Automatic gain is indicative of the processor output of digital signal being multiplied by a gain factor when the digital filter output included in the signal processor digital is below a setpoint value. When the signal of Automatic gain control output is received by a input phase and a quadrature converter (I / Q) -a- (logR / phi) connected to the signal processor digital, a corresponding value of the component of Signal radius calculated by the converter (I / Q) -a- (logR / phi). Because the processor of Conventional digital signal has 16 bits of input / output, the signal Automatic gain control output allows a signal input with a dynamic range and accuracy that exceeds 16 bits to be transferred from the digital signal processor without Loss of performance. As a result, a digital signal processor with a number of input / output bits less than normally required for accuracy and range Dynamic output signal.
La invención presente supera los problemas a los que se enfrenta las técnicas utilizadas actualmente mediante la compresión de una señal analógica de entrada en la banda base empleando una técnica logarítmica, convirtiendo la señal comprimida a un formato digital y expandiendo la señal digital a su escala lineal original utilizando una técnica antilogarítmica. El tamaño de la palabra de la señal digital expandida puede ser reducido mediante una técnica de normalización.The present invention overcomes problems to which faces the techniques currently used by the compression of an analog input signal in the baseband using a logarithmic technique, converting the compressed signal to a digital format and expanding the digital signal to its scale Original linear using an antilogarithmic technique. The size of the word of the expanded digital signal can be reduced by a standardization technique.
La Figura 1 es un diagrama de bloques de un control automático de ganancia de bucle cerrado de la técnica anterior.Figure 1 is a block diagram of a Automatic closed loop gain control technique previous.
La Figura 2 es un diagrama de bloques del control de ganancia automático completamente digital (ADGC) utilizando amplificadores logarítmicos reales como compresores y tablas de búsqueda antilogarítmicas (LUT) como expansores.Figure 2 is a block diagram of the fully digital automatic gain control (ADGC) using real logarithmic amplifiers as compressors and antilogarithmic search tables (LUT) as expanders.
La Figura 3 es un gráfico que describe el resultado de la compresión analógica y de la expansión digital.Figure 3 is a graph describing the result of analog compression and digital expansion.
La Figura 4 ilustra la mejora en rendimiento de un sistema de comunicaciones mediante una comparación entre el control de ganancia automático digital y el control automático de ganancia convencional.Figure 4 illustrates the improvement in performance of a communications system through a comparison between the Digital automatic gain control and automatic control of conventional gain
La Figura 1 muestra un circuito de control de ganancia automático 10 de bucle cerrado de la técnica anterior en el que las señales analógicas de entrada en fase (2) y de cuadratura (Q) están aplicadas respectivamente a los amplificadores 12 y 14. Las salidas de los mismos pasan por una conversión analógica a digital mediante los convertidores analógico/digital 16, 18 que se muestran en la figura como convertidores analógico/digital (por ejemplo de 6 bits), proporcionando las salidas I y Q en 16a y 18a, respectivamente.Figure 1 shows a control circuit of automatic gain 10 closed loop prior art in which the analog input signals in phase (2) and quadrature (Q) are applied respectively to amplifiers 12 and 14. Their outputs go through an analog conversion to digital using analog / digital converters 16, 18 which shown in the figure as analog / digital converters (for 6-bit example), providing outputs I and Q in 16th and 18th, respectively.
Las salidas de los convertidores analógico/digital 16 y 18 se aplican al circuito 20 para obtener la suma de I_{2} + Q_{2} que se compara a continuación con un nivel de referencia en el circuito de comparación 22. La salida del circuito de comparación 22 se transmite a un convertidor digital a analógico (DAC) 26 a través de un acumulador 24 y se aplica respectivamente a las entradas de control de ganancia 12b, 14b de los amplificadores de control de ganancia 12 y 14.The outputs of the converters analog / digital 16 and 18 are applied to circuit 20 to obtain the sum of I_ {2} + Q_ {2} which is then compared with a reference level in the comparison circuit 22. The output of the comparison circuit 22 is transmitted to a digital converter to analog (DAC) 26 through an accumulator 24 and applied respectively to the gain control inputs 12b, 14b of gain control amplifiers 12 and 14.
El dispositivo de control de ganancia completamente digital 30 (ADGC) de la invención presente evita algunos de los requisitos asociados con la naturaleza del sistema de circuitos de control de ganancia automática de circuito cerrado descrita más arriba, y cumple con los requisitos restantes sin demasiadas dificultades. La invención presente emplea un método de conversión analógico a digital que incrementa el número de bits ADC efectivos comprimiendo la señal analógica de entrada de banda base utilizando un compresor analógico, por ejemplo un sistema de circuitos logarítmico. El compresor analógico es un dispositivo no lineal en donde la ganancia es inversamente proporcional a la señal de entrada. Esto incrementa el rango dinámico de la señal de entrada analógica.The gain control device fully digital 30 (ADGC) of the present invention prevents some of the requirements associated with the nature of the system Automatic gain control circuit of closed circuit described above, and meets the remaining requirements without Too many difficulties The present invention employs a method of analog to digital conversion that increases the number of ADC bits effective by compressing the analog baseband input signal using an analog compressor, for example a system of logarithmic circuits The analog compressor is a device not linear where the gain is inversely proportional to the signal input This increases the dynamic range of the input signal. analogue
Una vez que la señal analógica comprimida se convierte en una señal digital, un expansor digital, por ejemplo un proceso antilogarítmico o una tabla de búsqueda (LUT), se utiliza para expandir la señal digital de nuevo a su escala lineal original. El expansor digital es un dispositivo no lineal en el que la ganancia es proporcional a la señal de entrada. El tamaño de palabra de la salida del expansor puede ser mayor que el tamaño de la palabra de entrada debido a la naturaleza del funcionamiento de la mayoría en los expansores. Para reducir el tamaño de la palabra de la señal digital para reiniciar el receptor, puede ser aplicado un mecanismo de normalización, que puede ser un bloque de control de nivel automático de bucle abierto o de bucle cerrado.Once the compressed analog signal is converts into a digital signal, a digital expander, for example a antilogarithmic process or a search table (LUT), is used to expand the digital signal back to its linear scale original. The digital expander is a non-linear device in which The gain is proportional to the input signal. The size of word of the expander output can be larger than the size of the input word due to the nature of the operation of most in expanders. To reduce the word size of the digital signal to reset the receiver, it can be applied a normalization mechanism, which can be a control block Automatic level open loop or closed loop.
La Figura 2 muestra un diagrama de bloques del dispositivo de control de ganancia automático digital 30 de la invención presente. El dispositivo de control de ganancia automático digital emplea los amplificadores logarítmicos 32, 34 para la amplificación logarítmica de las señales I y Q que a continuación son conducidas a los convertidores analógicos a digital 36, 38 (por ejemplo de 8 bits) tras lo cual son conducidas a las tablas de búsqueda antilogarítmicas (LUTS) 40 y 42 para expandir la señal digital y a continuación son conducidas a un filtro pasa baja (por ejemplo un filtro de raíz elevada al coseno de respuesta de impulso infinito (RRC + IIR)) 44, 46, cada uno de los cuales se utiliza como interpolador.Figure 2 shows a block diagram of the digital automatic gain control device 30 of the present invention. The automatic gain control device digital uses logarithmic amplifiers 32, 34 for the Logarithmic amplification of the I and Q signals below are driven to analog to digital converters 36, 38 (by 8-bit example) after which they are led to the tables of antilogarithmic search (LUTS) 40 and 42 to expand the signal digital and then are driven to a low pass filter (by example a root filter raised to the impulse response cosine infinity (RRC + IIR)) 44, 46, each of which is used as interpolator.
Las salidas de los filtros 44 y 46 se aplican al circuito 48 que determina la raíz cuadrada de la suma de I_{2} y IQ_{2}. La salida del circuito 48 se conduce al circuito 50 que determina las medidas medias de potencia combinada de ambos canales I y Q antes de reducir el número de bits de la señal digital. El circuito 50 utiliza la Ecuación 1 para determinar la potencia combinada media con un esquema de bloque a bloque como sigue:The outputs of filters 44 and 46 are applied to the circuit 48 that determines the square root of the sum of I_ {2} and IQ_ {2}. The output of circuit 48 is conducted to circuit 50 which determines the average measures of combined power of both channels I and Q before reducing the number of bits of the digital signal. He circuit 50 uses Equation 1 to determine the power combined medium with a block-to-block scheme as follows:
en donde n es el tamaño de bloque y subí es la muestra i-ésima de la salida del circuito 50 dentro del bloque. Las salidas de los filtros 44 y 46 son desfasadas mediante los circuitos de desfase 52 y 54 con n muestras al objeto de sincronizar el tiempo entre las salidas de los filtros 44 y 46 para permitir completar las funciones realizadas por los circuitos 48, 50 y 56. Como resultado, las salidas de 58 y 60 son, respectivamente,where n is the block size and I raised is the ith sample of the output of circuit 50 within the block. The outputs of filters 44 and 46 are offset by the offset circuits 52 and 54 with n samples for the purpose of synchronize the time between the outputs of filters 44 and 46 to allow to complete the functions performed by circuits 48, 50 and 56. As a result, the outputs of 58 and 60 are, respectively,
donde I_{k} y Q_{k} para k = 1, ..., n son las n-ésimas salidas desfasadas de muestra de 44 y 46, respectivamente.where I_ {k} and Q_ {k} for k = 1, ..., n are the n-th out-of-date sample outputs of 44 and 46, respectively.
De acuerdo con la invención presente, se pude conseguir fácilmente un rango dinámico instantáneo de 70 dB. Se pueden obtener otros 20 ó 30 dB adicionales apagando o encendiendo la LNA. El dispositivo de control de ganancia completamente digital 30 no requiere de ningún control de ganancia en la radio, proporcionando de esta manera beneficios en cuanto a costes y simplicidad. Se pueden soportar fácilmente grandes variaciones de potencia instantánea mediante el dispositivo de control de ganancia completamente digital 30. El dispositivo de control de ganancia completamente digital 30 proporciona también un buen soporte para las recepciones de alta velocidad y las transmisiones comprimidas. Más aún, gracias a que el dispositivo de control de ganancia completamente digital 30 de la invención presente es de bucle abierto, no hay problemas de estabilidad, no hay ajuste de tiempo y no hay sobredisparo. El control de ganancia completamente digital 30 no necesita tener conocimiento alguno sobre la sincronización del tiempo de la señal, lo que es muy importante en búsqueda de células, adquisición de códigos y en el modo de corrección de frecuencia en un sistema que utiliza tecnología TDD (división del tiempo dúplex).In accordance with the present invention, it was possible Easily achieve an instantaneous dynamic range of 70 dB. Be they can get another 20 or 30 dB additional by turning off or on the LNA. The fully digital gain control device 30 does not require any gain control on the radio, thus providing cost benefits and simplicity Large variations of instantaneous power through the gain control device fully digital 30. The gain control device fully digital 30 also provides good support for high speed receptions and compressed transmissions. Moreover, thanks to the gain control device fully digital 30 of the present invention is loop open, no stability problems, no time adjustment and There is no over shot. The fully digital gain control 30 you don't need to have any knowledge about the synchronization of signal time, which is very important in search of cells, code acquisition and in the correction mode of frequency in a system that uses TDD technology (division of duplex time).
El dispositivo de control de ganancia completamente digital 30 proporciona una compensación de la atenuación muy rápida sin distorsionar la envolvente de la señal, lo que ayuda a evitar los problemas sufridos con las velocidades altas y/o las tasas de datos altas, pero no cambia la fase de inserción del sistema.The gain control device fully digital 30 provides compensation for the very fast attenuation without distorting the signal envelope, which helps to avoid the problems suffered with the speeds high and / or high data rates, but does not change the phase of system insertion
El resultado de la compresión analógica y de la expansión digital se muestra en la Figura 3. En esta Figura la curva en escalera representa la relación de la entrada al compresor analógico con la salida del expansor digital. Es claro que, utilizando una compresión analógica y una técnica de expansión digital una señal con una magnitud muy pequeña puede ser cuantificada con un paso de cuantificación muy pequeño. Esto generará muy poco ruido de cuantificación, y como consecuencia, mejorará el rendimiento del receptor.The result of analog compression and digital expansion is shown in Figure 3. In this Figure the ladder curve represents the ratio of the input to the compressor analog with the digital expander output. It's clear that, using analog compression and an expansion technique digital a signal with a very small magnitude can be quantified with a very small quantification step. This will generate very little quantification noise, and as a consequence, It will improve receiver performance.
Para observar la mejora en rendimiento en un sistema de comunicaciones, se realiza una comparación entre el dispositivo de control de ganancia completamente digital 30 de la invención presente y un circuito de control de ganancia automático tradicional utilizando un banco de pruebas de simulación de recepción de tecnología TDD (división del tiempo dúplex) con un detector ideal multiusuario y un canal de ruido añadido gaussiano. El resultado de la simulación se muestra en la Figura 4. En este banco de pruebas, la señal de entrada se somete a una variación de potencia de 20 dB de canal a canal. Aquí podemos apreciar que el dispositivo de control de ganancia completamente digital 30 de la invención presente mejora el rendimiento del sistema en casi 2 dB con una tasa de error de bloque (BLER) = 0,01.To observe the improvement in performance in a communications system, a comparison is made between the fully digital gain control device 30 of the present invention and an automatic gain control circuit traditional using a simulation test bench of TDD (duplex time division) technology reception with a ideal multi-user detector and an added Gaussian noise channel. The simulation result is shown in Figure 4. In this test bench, the input signal is subjected to a variation of 20 dB power from channel to channel. Here we can appreciate that the fully digital gain control device 30 of the Present invention improves system performance by almost 2 dB with a block error rate (BLER) = 0.01.
Claims (8)
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| US330749 | 2002-12-27 | ||
| US10/330,749 US7233624B2 (en) | 2002-06-11 | 2002-12-27 | Method and system for all digital gain control |
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