ES248357U - Programmable interruption controller (Machine-translation by Google Translate, not legally binding) - Google Patents

Programmable interruption controller (Machine-translation by Google Translate, not legally binding)

Info

Publication number
ES248357U
ES248357U ES1980248357U ES248357U ES248357U ES 248357 U ES248357 U ES 248357U ES 1980248357 U ES1980248357 U ES 1980248357U ES 248357 U ES248357 U ES 248357U ES 248357 U ES248357 U ES 248357U
Authority
ES
Spain
Prior art keywords
prom
address
lines
interruptions
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES1980248357U
Other languages
Spanish (es)
Other versions
ES248357Y (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sociedad Iberica de Transmisiones Electricas SA SITRE
Original Assignee
Sociedad Iberica de Transmisiones Electricas SA SITRE
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sociedad Iberica de Transmisiones Electricas SA SITRE filed Critical Sociedad Iberica de Transmisiones Electricas SA SITRE
Priority to ES1980248357U priority Critical patent/ES248357Y/en
Publication of ES248357U publication Critical patent/ES248357U/en
Application granted granted Critical
Publication of ES248357Y publication Critical patent/ES248357Y/en
Expired legal-status Critical Current

Links

Landscapes

  • Programmable Controllers (AREA)

Abstract

Programmable interrupt controller, which having the purpose of generating a plurality of vector interruptions for a microprocessor, is essentially characterized by a receiver block of the address and control bus lines, associated with an address decoder and eight prom-type memories powered by consumption saving circuits, said prom memories receiving all the address lines, except a prom that includes the vectors of the plurality of interruptions, using a subset of the addressing lines to discriminate the selection of the prom memories, through a decoder block from three to eight, having provided an address changing circuit that receives and stores the possible interruption lines according to a preassigned priority and generating the corresponding interruption vector with the particularity of existing a chain of meters, in bcd code, which divides the base frequency of a clock, according to three possibilities, selectable by switch, accessing the interruptions of this clock to the circuit changed of directions as well as to "drivers" with tri-state control, through bistable circuits and existing two monostable circuits activators of corresponding led diodes in the presence of an interruption or addressing. (Machine-translation by Google Translate, not legally binding)
ES1980248357U 1980-02-05 1980-02-05 PROGRAMMABLE INTERRUPTION CONTROLLER Expired ES248357Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
ES1980248357U ES248357Y (en) 1980-02-05 1980-02-05 PROGRAMMABLE INTERRUPTION CONTROLLER

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES1980248357U ES248357Y (en) 1980-02-05 1980-02-05 PROGRAMMABLE INTERRUPTION CONTROLLER

Publications (2)

Publication Number Publication Date
ES248357U true ES248357U (en) 1980-05-01
ES248357Y ES248357Y (en) 1981-01-01

Family

ID=8406926

Family Applications (1)

Application Number Title Priority Date Filing Date
ES1980248357U Expired ES248357Y (en) 1980-02-05 1980-02-05 PROGRAMMABLE INTERRUPTION CONTROLLER

Country Status (1)

Country Link
ES (1) ES248357Y (en)

Also Published As

Publication number Publication date
ES248357Y (en) 1981-01-01

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