ES485246A1 - Un aparato mejorado para transferir ordenes de entrada-sali-da - Google Patents

Un aparato mejorado para transferir ordenes de entrada-sali-da

Info

Publication number
ES485246A1
ES485246A1 ES485246A ES485246A ES485246A1 ES 485246 A1 ES485246 A1 ES 485246A1 ES 485246 A ES485246 A ES 485246A ES 485246 A ES485246 A ES 485246A ES 485246 A1 ES485246 A1 ES 485246A1
Authority
ES
Spain
Prior art keywords
input
command
channel
output
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES485246A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES485246A1 publication Critical patent/ES485246A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)
  • Computer And Data Communications (AREA)

Abstract

El presente invento crea medios para reducir el estado de sobrecarga de los adaptadores de entrada salida en cuanto a la aceptación de todas las órdenes de canal inmediatamente, sin un aumento importante en circuitos de almacenamiento intermedio o de control. Con el presente invento, una orden de canal puede ser tratada indistintamente como orden inmediata, la orden es admitida y ejecutada por el canal y el adaptador de entrada salida sin retardo.
ES485246A 1978-10-23 1979-10-22 Un aparato mejorado para transferir ordenes de entrada-sali-da Expired ES485246A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/954,070 US4224667A (en) 1978-10-23 1978-10-23 Command queuing for I/O adapters

Publications (1)

Publication Number Publication Date
ES485246A1 true ES485246A1 (es) 1980-05-16

Family

ID=25494892

Family Applications (1)

Application Number Title Priority Date Filing Date
ES485246A Expired ES485246A1 (es) 1978-10-23 1979-10-22 Un aparato mejorado para transferir ordenes de entrada-sali-da

Country Status (8)

Country Link
US (1) US4224667A (es)
EP (1) EP0010187B1 (es)
JP (1) JPS5559528A (es)
AU (1) AU527907B2 (es)
BR (1) BR7906843A (es)
CA (1) CA1119308A (es)
DE (1) DE2965381D1 (es)
ES (1) ES485246A1 (es)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4445176A (en) * 1979-12-28 1984-04-24 International Business Machines Corporation Block transfers of information in data processing networks
US4546430A (en) * 1983-07-13 1985-10-08 Sperry Corporation Control unit busy queuing
GB2162709A (en) * 1984-06-22 1986-02-05 Hitachi Ltd A magnetic bubble memory
JPH0644251B2 (ja) * 1986-08-28 1994-06-08 日本電気株式会社 デ−タ処理装置
US4837738A (en) * 1986-11-05 1989-06-06 Honeywell Information Systems Inc. Address boundary detector
US5155812A (en) * 1989-05-04 1992-10-13 Texas Instruments Incorporated Devices and method for generating and using systems, software waitstates on address boundaries in data processing
US5065313A (en) * 1989-03-30 1991-11-12 Dell Usa Corporation Digital computer system having circuit for regulation of I/O command recovery time
US5617574A (en) 1989-05-04 1997-04-01 Texas Instruments Incorporated Devices, systems and methods for conditional instructions
US5386560A (en) * 1991-05-23 1995-01-31 International Business Machines Corporation Execution of page data transfer by PT processors and issuing of split start and test instructions by CPUs coordinated by queued tokens
US5548791A (en) * 1994-07-25 1996-08-20 International Business Machines Corporation Input/output control system with plural channel paths to I/O devices
US5822611A (en) * 1995-06-05 1998-10-13 Donley; Greggory D. Method for cycle request with quick termination without waiting for the cycle to reach the destination by storing information in queue
JP4086345B2 (ja) * 1997-09-09 2008-05-14 キヤノン株式会社 通信制御方法及び装置及び通信システム
US10310923B1 (en) 2014-08-28 2019-06-04 Seagate Technology Llc Probabilistic aging command sorting
US10831403B2 (en) 2017-05-19 2020-11-10 Seagate Technology Llc Probabalistic command aging and selection
CN108833056B (zh) * 2018-05-23 2021-02-23 江苏格澜得智能电气有限公司 一种消防两总线优先通信的编码方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3514758A (en) * 1967-03-27 1970-05-26 Burroughs Corp Digital computer system having multi-line control unit
US3566358A (en) * 1968-03-19 1971-02-23 Bevier Hasbrouck Integrated multi-computer system
US3623006A (en) * 1970-06-29 1971-11-23 Burroughs Corp Queueing device for the selection of requests for access to a storage medium
US3688274A (en) * 1970-12-23 1972-08-29 Ibm Command retry control by peripheral devices
US3725864A (en) * 1971-03-03 1973-04-03 Ibm Input/output control
JPS4938530A (es) * 1972-06-30 1974-04-10
DE2237576C3 (de) * 1972-07-31 1980-10-30 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren und Anordnung zur Übertragung von Informationen zwischen peripheren Geraten und dem Arbeitsspeicher einer Zentraleinheit über einen Blockmultiplexkanal
US3961312A (en) * 1974-07-15 1976-06-01 International Business Machines Corporation Cycle interleaving during burst mode operation
US3993981A (en) * 1975-06-30 1976-11-23 Honeywell Information Systems, Inc. Apparatus for processing data transfer requests in a data processing system

Also Published As

Publication number Publication date
CA1119308A (en) 1982-03-02
AU5055979A (en) 1980-05-01
JPS5732364B2 (es) 1982-07-10
JPS5559528A (en) 1980-05-06
US4224667A (en) 1980-09-23
AU527907B2 (en) 1983-03-31
BR7906843A (pt) 1980-09-16
DE2965381D1 (en) 1983-06-16
EP0010187B1 (en) 1983-05-11
EP0010187A1 (en) 1980-04-30

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19970519