ES8107403A1 - Un circuito libre de fallos para interrogar un almacenaje enmatriz - Google Patents

Un circuito libre de fallos para interrogar un almacenaje enmatriz

Info

Publication number
ES8107403A1
ES8107403A1 ES494111A ES494111A ES8107403A1 ES 8107403 A1 ES8107403 A1 ES 8107403A1 ES 494111 A ES494111 A ES 494111A ES 494111 A ES494111 A ES 494111A ES 8107403 A1 ES8107403 A1 ES 8107403A1
Authority
ES
Spain
Prior art keywords
matrix
computers
failures
translation
check
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES494111A
Other languages
English (en)
Other versions
ES494111A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Spain SA
Original Assignee
Alcatel Espana SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Espana SA filed Critical Alcatel Espana SA
Publication of ES494111A0 publication Critical patent/ES494111A0/es
Publication of ES8107403A1 publication Critical patent/ES8107403A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/74—Masking faults in memories by using spares or by reconfiguring using duplex memories, i.e. using dual copies
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L21/00—Station blocking between signal boxes in one yard
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/22—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling
    • G06F13/225—Handling requests for interconnection or transfer for access to input/output bus using successive scanning, e.g. polling with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Storage Device Security (AREA)
  • Debugging And Monitoring (AREA)

Abstract

CIRCUITO DUPLICADO PARA EVITAR FALLOS EN SISTEMAS DE INTERROGACION DE MATRICES CON INFORMACION. DOS MATRICES (MA, MB), CON IDENTICO CONTENIDO DE ALMACENAJE, TIENE SUS TERMINALES DE COLUMNA CONECTADOS EN PARALELO A TODOS LOS COMPUTADORES (RA1 A RA4, RB1 A RB4), DIVIDIDOS EN DOS GRUPOS, Y LOS TERMINALES FILA VAN A, POR LO MENOS, UN COMPUTADOR DE CADA GRUPO. EL ACCESO DE LOS COMPUTADORES (RA1 ..., RB4) A LAS MATRICES (MA, MB) TIENE LUGAR A TRAVES DE UNOS DECODIFICADORES (DAA, DAB, DBA, DBB) CON CIRCUITOS DE PRIORIDAD (PAA, PAB, PBA, PBB) ASOCIADOS DE SELECCION.
ES494111A 1979-08-09 1980-08-08 Un circuito libre de fallos para interrogar un almacenaje enmatriz Expired ES8107403A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2932271A DE2932271C2 (de) 1979-08-09 1979-08-09 Schaltungsanordnung zur signaltechnisch sicheren Abfrage eines Matrixspeichers

Publications (2)

Publication Number Publication Date
ES494111A0 ES494111A0 (es) 1981-10-16
ES8107403A1 true ES8107403A1 (es) 1981-10-16

Family

ID=6078009

Family Applications (1)

Application Number Title Priority Date Filing Date
ES494111A Expired ES8107403A1 (es) 1979-08-09 1980-08-08 Un circuito libre de fallos para interrogar un almacenaje enmatriz

Country Status (7)

Country Link
AT (1) AT374297B (es)
CH (1) CH649163A5 (es)
DE (1) DE2932271C2 (es)
ES (1) ES8107403A1 (es)
IL (1) IL60736A (es)
SE (1) SE441223B (es)
YU (1) YU41727B (es)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3668644A (en) * 1970-02-09 1972-06-06 Burroughs Corp Failsafe memory system

Also Published As

Publication number Publication date
ATA386480A (de) 1983-08-15
YU41727B (en) 1987-12-31
IL60736A (en) 1984-10-31
SE8005458L (sv) 1981-02-10
ES494111A0 (es) 1981-10-16
YU200480A (en) 1982-08-31
SE441223B (sv) 1985-09-16
DE2932271A1 (de) 1981-02-12
CH649163A5 (en) 1985-04-30
IL60736A0 (en) 1980-10-26
AT374297B (de) 1984-04-10
DE2932271C2 (de) 1981-12-24

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19970401