ES8405172A1 - "una disposicion de circuito para el control de la transmision cuasisincrona de datos" - Google Patents

"una disposicion de circuito para el control de la transmision cuasisincrona de datos"

Info

Publication number
ES8405172A1
ES8405172A1 ES523535A ES523535A ES8405172A1 ES 8405172 A1 ES8405172 A1 ES 8405172A1 ES 523535 A ES523535 A ES 523535A ES 523535 A ES523535 A ES 523535A ES 8405172 A1 ES8405172 A1 ES 8405172A1
Authority
ES
Spain
Prior art keywords
circuit arrangement
processor
data
quasi
controlling
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES523535A
Other languages
English (en)
Other versions
ES523535A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Voestalpine AG
Original Assignee
Voestalpine AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Voestalpine AG filed Critical Voestalpine AG
Publication of ES8405172A1 publication Critical patent/ES8405172A1/es
Publication of ES523535A0 publication Critical patent/ES523535A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/143—Two-way operation using the same type of signal, i.e. duplex for modulated signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

DISPOSICION DE CIRCUITO PARA EL CONTROL DE LA TRANSMISION CUASISINCRONA DE DATOS.LA DISPOSICION ESTA COLOCADA ENTRE UNA UNIDAD EMISORA O RECEPTORA DE DATOS, TAL COMO UN ORDENADOR O UN TERMINAL (2), Y UN MODEM (5), Y CONTIENE UN PROCESADOR. LA SALIDA EN PARALELO DEL PROCESADOR O DE UN MICROPROCESADOR (10), PARA EL QUE ESTA PREVISTO DISPONER DE UN GENERADOR PROPIO DE SINCRONISMO EXACTO (9), CONTIENE CONEXIONES PARA LINEAS DE SEÑAL DEL MODEM POR LAS QUE SON APORTADAS AL PROCESADOR O AL MICROORDENADOR SEÑALES RELATIVAS AL ESTADO DE OCUPACION O A LA CALIDADDE LA TRANSMISION.
ES523535A 1982-06-24 1983-06-23 "una disposicion de circuito para el control de la transmision cuasisincrona de datos" Granted ES523535A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
AT245982 1982-06-24

Publications (2)

Publication Number Publication Date
ES8405172A1 true ES8405172A1 (es) 1984-05-16
ES523535A0 ES523535A0 (es) 1984-05-16

Family

ID=3534745

Family Applications (1)

Application Number Title Priority Date Filing Date
ES523535A Granted ES523535A0 (es) 1982-06-24 1983-06-23 "una disposicion de circuito para el control de la transmision cuasisincrona de datos"

Country Status (6)

Country Link
EP (1) EP0098259B1 (es)
DE (1) DE3377762D1 (es)
ES (1) ES523535A0 (es)
FI (1) FI832299A7 (es)
NO (1) NO832298L (es)
PT (1) PT76884B (es)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1021004B (it) * 1973-11-09 1978-01-30 Honeywell Inf Systems Apparecchiatura elettronica di co mando di periferica per il collega mento locale e remoto della stessa ad un sistema di elaborazione dati
FR2404970A1 (fr) * 1977-10-03 1979-04-27 Sfena Systeme de couplage pour transmission en duplex de donnees numeriques entre deux unites de traitement
IT1146176B (it) * 1980-02-07 1986-11-12 Italdata Spa Dispositivo interfacciale per la gestione automatica di una linea telefonica commutata

Also Published As

Publication number Publication date
FI832299L (fi) 1983-12-25
NO832298L (no) 1983-12-27
FI832299A0 (fi) 1983-06-22
PT76884B (en) 1986-01-27
EP0098259B1 (de) 1988-08-17
PT76884A (en) 1983-07-01
EP0098259A2 (de) 1984-01-11
EP0098259A3 (en) 1985-10-09
ES523535A0 (es) 1984-05-16
FI832299A7 (fi) 1983-12-25
DE3377762D1 (en) 1988-09-22

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19980102