ES8407635A1 - Una instalacion de arbitraje de via de transmision - Google Patents

Una instalacion de arbitraje de via de transmision

Info

Publication number
ES8407635A1
ES8407635A1 ES527271A ES527271A ES8407635A1 ES 8407635 A1 ES8407635 A1 ES 8407635A1 ES 527271 A ES527271 A ES 527271A ES 527271 A ES527271 A ES 527271A ES 8407635 A1 ES8407635 A1 ES 8407635A1
Authority
ES
Spain
Prior art keywords
data processing
signal
bus arbitration
bus
poll
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES527271A
Other languages
English (en)
Other versions
ES527271A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES8407635A1 publication Critical patent/ES8407635A1/es
Publication of ES527271A0 publication Critical patent/ES527271A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/37—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

INSTALACION DE ARBITRAJE DE VIA DE TRANSMISION PARA ESTABLECER, EN CICLOS DE VIA DE TRANSMISION SUCESIVOS, EL ESCRUTINIO Y LA INTERCONEXION DE DISPOSITIVOS ASIGNADOS A UNA VIA DE TRANSMISION EN UNA INSTALACION DE TRATAMIENTO DE DATOS.CONSTA DE UN DISPOSITIVO DE ARBITRAJE DE VIA DE TRANSMISION PARA RECIBIR SEÑALES DE PETICION PARA SERVICIO Y PARA SUMINISTRAR UNA SEÑAL DE ACUSE DE RECIBO; DE UNA PLURALIDAD DE UNIDADES DE VIA DE TRANSMISION; Y DE MEDIOS DE INTERCONEXION PARA INTERCONECTAR EL DISPOSITIVO DE ARBITRAJE DE VIA DE TRANSMISION Y LAS UNIDADES DE VIA DETRANSMISION.
ES527271A 1982-12-20 1983-11-15 Una instalacion de arbitraje de via de transmision Granted ES527271A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US45088682A 1982-12-20 1982-12-20

Publications (2)

Publication Number Publication Date
ES8407635A1 true ES8407635A1 (es) 1984-09-16
ES527271A0 ES527271A0 (es) 1984-09-16

Family

ID=23789913

Family Applications (1)

Application Number Title Priority Date Filing Date
ES527271A Granted ES527271A0 (es) 1982-12-20 1983-11-15 Una instalacion de arbitraje de via de transmision

Country Status (8)

Country Link
EP (1) EP0114928B1 (es)
JP (1) JPS59114624A (es)
AU (1) AU558825B2 (es)
BR (1) BR8306942A (es)
CA (1) CA1199416A (es)
DE (1) DE3375048D1 (es)
ES (1) ES527271A0 (es)
MX (1) MX154710A (es)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8419641D0 (en) * 1984-08-01 1984-09-05 Firstquad Ltd Computer printer scheduler
US4809164A (en) * 1986-03-26 1989-02-28 Tandem Computers Incorporated Processor controlled modifying of tabled input/output priority
DE4407895C2 (de) * 1994-03-10 1997-05-22 Reko Electronic Gmbh Verfahren zur Konfiguration eines Informationsdatennetzes
US9946665B2 (en) * 2011-05-13 2018-04-17 Melange Systems Private Limited Fetch less instruction processing (FLIP) computer architecture for central processing units (CPU)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3997896A (en) * 1975-06-30 1976-12-14 Honeywell Information Systems, Inc. Data processing system providing split bus cycle operation
US4059851A (en) * 1976-07-12 1977-11-22 Ncr Corporation Priority network for devices coupled by a common bus

Also Published As

Publication number Publication date
EP0114928A1 (en) 1984-08-08
ES527271A0 (es) 1984-09-16
JPS59114624A (ja) 1984-07-02
AU2185183A (en) 1984-06-28
MX154710A (es) 1987-12-02
DE3375048D1 (en) 1988-02-04
CA1199416A (en) 1986-01-14
AU558825B2 (en) 1987-02-12
BR8306942A (pt) 1984-07-24
EP0114928B1 (en) 1987-12-23

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19970303