FI20095937L - Menetelmä sisäisten mekaanisten jännitysten vähentämiseksi puolijohderakenteessa ja puolijohderakenne, jossa on matalat mekaaniset jännitykset - Google Patents

Menetelmä sisäisten mekaanisten jännitysten vähentämiseksi puolijohderakenteessa ja puolijohderakenne, jossa on matalat mekaaniset jännitykset Download PDF

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Publication number
FI20095937L
FI20095937L FI20095937A FI20095937A FI20095937L FI 20095937 L FI20095937 L FI 20095937L FI 20095937 A FI20095937 A FI 20095937A FI 20095937 A FI20095937 A FI 20095937A FI 20095937 L FI20095937 L FI 20095937L
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FI
Finland
Prior art keywords
semiconductor structure
mechanical stresses
reducing internal
low mechanical
low
Prior art date
Application number
FI20095937A
Other languages
English (en)
Swedish (sv)
Other versions
FI123319B (fi
FI20095937A0 (fi
Inventor
Alexei Romanov
Maxim A Odnoblyudov
Vladislav V Bougrov
Original Assignee
Optogan Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Optogan Oy filed Critical Optogan Oy
Publication of FI20095937A0 publication Critical patent/FI20095937A0/fi
Priority to FI20095937A priority Critical patent/FI123319B/fi
Priority to PCT/FI2010/050696 priority patent/WO2011030001A1/en
Priority to RU2012112370/28A priority patent/RU2012112370A/ru
Priority to KR1020127009230A priority patent/KR20120099007A/ko
Priority to JP2012528400A priority patent/JP2013504865A/ja
Priority to US13/395,496 priority patent/US20120241755A1/en
Priority to TW099130430A priority patent/TW201133555A/zh
Priority to EP10815046.7A priority patent/EP2476134A4/en
Priority to CN2010800400288A priority patent/CN102714136A/zh
Publication of FI20095937L publication Critical patent/FI20095937L/fi
Application granted granted Critical
Publication of FI123319B publication Critical patent/FI123319B/fi

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/27—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials
    • H10P14/276—Lateral overgrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2921—Materials being crystalline insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2926—Crystal orientations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
    • H10P14/3216—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3416—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
FI20095937A 2009-09-10 2009-09-10 Menetelmä sisäisten mekaanisten jännitysten vähentämiseksi puolijohderakenteessa ja puolijohderakenne, jossa on vähän mekaanisia jännityksiä FI123319B (fi)

Priority Applications (9)

Application Number Priority Date Filing Date Title
FI20095937A FI123319B (fi) 2009-09-10 2009-09-10 Menetelmä sisäisten mekaanisten jännitysten vähentämiseksi puolijohderakenteessa ja puolijohderakenne, jossa on vähän mekaanisia jännityksiä
JP2012528400A JP2013504865A (ja) 2009-09-10 2010-09-09 半導体構造の内部機械応力を減少させる方法および機械応力の小さい半導体構造
RU2012112370/28A RU2012112370A (ru) 2009-09-10 2010-09-09 Способ снижения внутренних механических рапряжений в полупроводниковой структуре и полупроводниковая структура с низкими механическими напряжениями
KR1020127009230A KR20120099007A (ko) 2009-09-10 2010-09-09 반도체 구조물에서 내부 기계응력의 감소 방법 및 저 기계응력 반도체 구조물
PCT/FI2010/050696 WO2011030001A1 (en) 2009-09-10 2010-09-09 A method for reducing internal mechanical stresses in a semiconductor structure and a low mechanical stress semiconductor structure
US13/395,496 US20120241755A1 (en) 2009-09-10 2010-09-09 method for reducing internal mechanical stresses in a semiconductor structure and a low mechanical stress semiconductor structure
TW099130430A TW201133555A (en) 2009-09-10 2010-09-09 A method for reducing internal mechanical stresses in a semiconductor structure and a low mechanical stress semiconductor structure
EP10815046.7A EP2476134A4 (en) 2009-09-10 2010-09-09 METHOD FOR REDUCING INTERNAL MECHANICAL LOADS IN A SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR STRUCTURE WITH LOW MECHANICAL LOAD
CN2010800400288A CN102714136A (zh) 2009-09-10 2010-09-09 用于降低半导体结构中的内部机械应力的方法以及低机械应力半导体结构

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20095937 2009-09-10
FI20095937A FI123319B (fi) 2009-09-10 2009-09-10 Menetelmä sisäisten mekaanisten jännitysten vähentämiseksi puolijohderakenteessa ja puolijohderakenne, jossa on vähän mekaanisia jännityksiä

Publications (3)

Publication Number Publication Date
FI20095937A0 FI20095937A0 (fi) 2009-09-10
FI20095937L true FI20095937L (fi) 2011-03-11
FI123319B FI123319B (fi) 2013-02-28

Family

ID=41136399

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20095937A FI123319B (fi) 2009-09-10 2009-09-10 Menetelmä sisäisten mekaanisten jännitysten vähentämiseksi puolijohderakenteessa ja puolijohderakenne, jossa on vähän mekaanisia jännityksiä

Country Status (9)

Country Link
US (1) US20120241755A1 (fi)
EP (1) EP2476134A4 (fi)
JP (1) JP2013504865A (fi)
KR (1) KR20120099007A (fi)
CN (1) CN102714136A (fi)
FI (1) FI123319B (fi)
RU (1) RU2012112370A (fi)
TW (1) TW201133555A (fi)
WO (1) WO2011030001A1 (fi)

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US9859457B2 (en) * 2008-03-27 2018-01-02 Nitek, Inc. Semiconductor and template for growing semiconductors
CN102427100A (zh) * 2011-11-11 2012-04-25 郭磊 半导体结构及其形成方法
CN103247724B (zh) * 2012-02-08 2016-04-20 郭磊 一种半导体结构及其形成方法
CN103247725B (zh) * 2012-02-08 2016-01-20 郭磊 一种半导体结构及其形成方法
WO2013117153A1 (en) * 2012-02-08 2013-08-15 Lei Guo Semiconductor structure and method for forming same
CN103247516B (zh) * 2012-02-08 2016-04-06 郭磊 一种半导体结构及其形成方法
EP2693462B1 (en) 2012-07-31 2016-06-01 Imec Method for manufacturing semiconductor devices
US9064699B2 (en) 2013-09-30 2015-06-23 Samsung Electronics Co., Ltd. Methods of forming semiconductor patterns including reduced dislocation defects and devices formed using such methods
JP6212203B2 (ja) 2014-04-14 2017-10-11 住友化学株式会社 窒化物半導体単結晶基板の製造方法
WO2015193955A1 (ja) * 2014-06-16 2015-12-23 株式会社サイオクス 窒化物半導体単結晶基板の製造方法
CN105336603A (zh) * 2014-07-28 2016-02-17 中芯国际集成电路制造(上海)有限公司 复合氧化膜结构
CN105448648B (zh) * 2014-07-30 2018-09-25 北大方正集团有限公司 一种晶片流片方法
TWI602220B (zh) * 2015-03-04 2017-10-11 國立成功大學 磊晶模具及磊晶方法
CN107093657B (zh) * 2017-05-08 2019-02-22 河北工业大学 一种薄膜腔体型图形衬底及其制备方法
GB2586862B (en) * 2019-09-06 2021-12-15 Plessey Semiconductors Ltd LED precursor incorporating strain relaxing structure
EP3812487A1 (en) 2019-10-25 2021-04-28 Xie, Fengjie Non-polar iii-nitride binary and ternary materials, method for obtaining thereof and uses
CN110783176B (zh) * 2019-10-30 2022-07-12 广西大学 一种低应力半导体材料制备方法
EP4044216A1 (en) 2021-02-16 2022-08-17 Siltronic AG Method for testing the stress robustness of a semiconductor substrate

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JP3696003B2 (ja) * 1999-09-22 2005-09-14 三洋電機株式会社 窒化物系半導体層の形成方法
JP4432180B2 (ja) * 1999-12-24 2010-03-17 豊田合成株式会社 Ｉｉｉ族窒化物系化合物半導体の製造方法、ｉｉｉ族窒化物系化合物半導体素子及びｉｉｉ族窒化物系化合物半導体
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Also Published As

Publication number Publication date
FI123319B (fi) 2013-02-28
RU2012112370A (ru) 2013-10-20
JP2013504865A (ja) 2013-02-07
WO2011030001A1 (en) 2011-03-17
FI20095937A0 (fi) 2009-09-10
EP2476134A1 (en) 2012-07-18
KR20120099007A (ko) 2012-09-06
US20120241755A1 (en) 2012-09-27
TW201133555A (en) 2011-10-01
EP2476134A4 (en) 2014-10-08
CN102714136A (zh) 2012-10-03

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