FR2282162A1 - Procede de realisation de dispositifs semiconducteurs - Google Patents
Procede de realisation de dispositifs semiconducteursInfo
- Publication number
- FR2282162A1 FR2282162A1 FR7427905A FR7427905A FR2282162A1 FR 2282162 A1 FR2282162 A1 FR 2282162A1 FR 7427905 A FR7427905 A FR 7427905A FR 7427905 A FR7427905 A FR 7427905A FR 2282162 A1 FR2282162 A1 FR 2282162A1
- Authority
- FR
- France
- Prior art keywords
- semiconductor devices
- semiconductor
- devices
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
- H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/037—Diffusion-deposition
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/102—Mask alignment
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/106—Masks, special
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/136—Resistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/151—Simultaneous diffusion
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/975—Substrate or mask aligning feature
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7427905A FR2282162A1 (fr) | 1974-08-12 | 1974-08-12 | Procede de realisation de dispositifs semiconducteurs |
| US05/598,015 US4009057A (en) | 1974-08-12 | 1975-07-22 | Method of manufacturing a semiconductor device |
| DE2534132A DE2534132C3 (de) | 1974-08-12 | 1975-07-31 | Verfahren zur Herstellung einer Halbleiteranordnung |
| CA233,170A CA1035471A (fr) | 1974-08-12 | 1975-08-07 | Mode de fabrication de semiconducteurs par empreinte de masque |
| NL7509464A NL7509464A (nl) | 1974-08-12 | 1975-08-08 | Werkwijze voor het vervaardigen van een half- geleiderinrichting. |
| GB33182/75A GB1515184A (en) | 1974-08-12 | 1975-08-08 | Semiconductor device manufacture |
| JP50096322A JPS5142476A (en) | 1974-08-12 | 1975-08-09 | Handotaisochino seizohoho |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7427905A FR2282162A1 (fr) | 1974-08-12 | 1974-08-12 | Procede de realisation de dispositifs semiconducteurs |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2282162A1 true FR2282162A1 (fr) | 1976-03-12 |
| FR2282162B1 FR2282162B1 (fr) | 1978-04-28 |
Family
ID=9142340
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7427905A Granted FR2282162A1 (fr) | 1974-08-12 | 1974-08-12 | Procede de realisation de dispositifs semiconducteurs |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US4009057A (fr) |
| JP (1) | JPS5142476A (fr) |
| CA (1) | CA1035471A (fr) |
| DE (1) | DE2534132C3 (fr) |
| FR (1) | FR2282162A1 (fr) |
| GB (1) | GB1515184A (fr) |
| NL (1) | NL7509464A (fr) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0183624A3 (fr) * | 1984-11-28 | 1988-03-02 | Fairchild Semiconductor Corporation | Procédé de fabrication de circuits intégrés bipolaires analogiques à haute densité d'intégration à grande vitesse |
| EP0339315A1 (fr) * | 1988-04-28 | 1989-11-02 | Fujitsu Limited | Méthode de fabrication de dispositifs semi-conducteurs protégés contre la contamination due aux étapes de configuration |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4151019A (en) * | 1974-12-27 | 1979-04-24 | Tokyo Shibaura Electric Co., Ltd. | Method of manufacturing integrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques |
| US4153487A (en) * | 1974-12-27 | 1979-05-08 | Tokyo Shibaura Electric Co., Ltd. | Method of manufacturing intergrated injection logic semiconductor devices utilizing self-aligned double-diffusion techniques |
| US4110126A (en) * | 1977-08-31 | 1978-08-29 | International Business Machines Corporation | NPN/PNP Fabrication process with improved alignment |
| US4118250A (en) * | 1977-12-30 | 1978-10-03 | International Business Machines Corporation | Process for producing integrated circuit devices by ion implantation |
| US4201800A (en) * | 1978-04-28 | 1980-05-06 | International Business Machines Corp. | Hardened photoresist master image mask process |
| US4244752A (en) * | 1979-03-06 | 1981-01-13 | Burroughs Corporation | Single mask method of fabricating complementary integrated circuits |
| US5219770A (en) * | 1983-11-30 | 1993-06-15 | Fujitsu Limited | Method for fabricating a MISFET including a common contact window |
| US4829018A (en) * | 1986-06-27 | 1989-05-09 | Wahlstrom Sven E | Multilevel integrated circuits employing fused oxide layers |
| US4843026A (en) * | 1987-09-24 | 1989-06-27 | Intel Corporation | Architecture modification for improved ROM security |
| JPH06101540B2 (ja) * | 1989-05-19 | 1994-12-12 | 三洋電機株式会社 | 半導体集積回路の製造方法 |
| EP0562309B1 (fr) * | 1992-03-25 | 2002-06-12 | Texas Instruments Incorporated | Procédé planaire utilisant des marques d'alignement communes pour les implantations de puit |
| KR102762200B1 (ko) * | 2022-10-27 | 2025-02-03 | 이재호 | 배수구 커버 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2160667A1 (fr) * | 1971-11-20 | 1973-06-29 | Itt |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3697318A (en) * | 1967-05-23 | 1972-10-10 | Ibm | Monolithic integrated structure including fabrication thereof |
| US3640782A (en) * | 1967-10-13 | 1972-02-08 | Gen Electric | Diffusion masking in semiconductor preparation |
| US3560278A (en) * | 1968-11-29 | 1971-02-02 | Motorola Inc | Alignment process for fabricating semiconductor devices |
| GB1355806A (en) * | 1970-12-09 | 1974-06-05 | Mullard Ltd | Methods of manufacturing a semiconductor device |
| JPS5538823B2 (fr) * | 1971-12-22 | 1980-10-07 | ||
| GB1384028A (en) * | 1972-08-21 | 1974-02-12 | Hughes Aircraft Co | Method of making a semiconductor device |
| US3793088A (en) * | 1972-11-15 | 1974-02-19 | Bell Telephone Labor Inc | Compatible pnp and npn devices in an integrated circuit |
-
1974
- 1974-08-12 FR FR7427905A patent/FR2282162A1/fr active Granted
-
1975
- 1975-07-22 US US05/598,015 patent/US4009057A/en not_active Expired - Lifetime
- 1975-07-31 DE DE2534132A patent/DE2534132C3/de not_active Expired
- 1975-08-07 CA CA233,170A patent/CA1035471A/fr not_active Expired
- 1975-08-08 GB GB33182/75A patent/GB1515184A/en not_active Expired
- 1975-08-08 NL NL7509464A patent/NL7509464A/xx not_active Application Discontinuation
- 1975-08-09 JP JP50096322A patent/JPS5142476A/ja active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2160667A1 (fr) * | 1971-11-20 | 1973-06-29 | Itt |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0183624A3 (fr) * | 1984-11-28 | 1988-03-02 | Fairchild Semiconductor Corporation | Procédé de fabrication de circuits intégrés bipolaires analogiques à haute densité d'intégration à grande vitesse |
| EP0339315A1 (fr) * | 1988-04-28 | 1989-11-02 | Fujitsu Limited | Méthode de fabrication de dispositifs semi-conducteurs protégés contre la contamination due aux étapes de configuration |
| US5132252A (en) * | 1988-04-28 | 1992-07-21 | Fujitsu Limited | Method for fabricating semiconductor devices that prevents pattern contamination |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2534132C3 (de) | 1978-06-01 |
| DE2534132A1 (de) | 1976-02-26 |
| GB1515184A (en) | 1978-06-21 |
| DE2534132B2 (de) | 1977-10-13 |
| US4009057A (en) | 1977-02-22 |
| CA1035471A (fr) | 1978-07-25 |
| JPS5319900B2 (fr) | 1978-06-23 |
| FR2282162B1 (fr) | 1978-04-28 |
| NL7509464A (nl) | 1976-02-16 |
| JPS5142476A (en) | 1976-04-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |