FR2425110A1 - ANTEMEMORY DATA PROCESSING SYSTEM - Google Patents

ANTEMEMORY DATA PROCESSING SYSTEM

Info

Publication number
FR2425110A1
FR2425110A1 FR7832892A FR7832892A FR2425110A1 FR 2425110 A1 FR2425110 A1 FR 2425110A1 FR 7832892 A FR7832892 A FR 7832892A FR 7832892 A FR7832892 A FR 7832892A FR 2425110 A1 FR2425110 A1 FR 2425110A1
Authority
FR
France
Prior art keywords
antememory
directory
groups
processing unit
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7832892A
Other languages
French (fr)
Other versions
FR2425110B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/853,982 external-priority patent/US4156906A/en
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of FR2425110A1 publication Critical patent/FR2425110A1/en
Application granted granted Critical
Publication of FR2425110B1 publication Critical patent/FR2425110B1/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/3016—Decoding the operand specifier, e.g. specifier format
    • G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)

Abstract

LE SYSTEME COMPREND UNE MEMOIRE PRINCIPALE RELIEE A UNE UNITE DE TRAITEMENT PAR UNE ANTEMEMOIRE COMPORTANT DES GROUPES D'EMPLACEMENTS DE MOTS, UN REPERTOIRE DE DONNEES SERVANT A MEMORISER DES ADRESSES DANS DES EMPLACEMENTS CORRESPONDANT AU NOMBRE DESDITS GROUPES, UN REPERTOIRE DE COMMANDE COMPRENANT UN NOMBRE DE BITS CORRESPONDANT AU NOMBRE DE GROUPES, ET UN TAMPON DE COMMANDE D'ENTREE POUR MEMORISER DES DEMANDES RECUES DE L'UNITE DE TRAITEMENT ET DE CIRCUITS DE COMMANDE QUI COMPRENNENT UN DECODEUR METTANT A UN ETAT PREDETERMINE UN BIT DEFINI DU REPERTOIRE DE COMMANDE QUAND LE REPERTOIRE DE DONNEES INDIQUE QUE LE MOT DEMANDE NE SE TROUVE PAS DANS L'ANTEMEMOIRE. APPLICATION AUX SYSTEMES DE TRAITEMENT MICROPROGRAMMES.THE SYSTEM INCLUDES A MAIN MEMORY LINKED TO A PROCESSING UNIT BY A MEMORY INCLUDING GROUPS OF WORD LOCATIONS, A DATA DIRECTORY SERVING TO STORE ADDRESSES IN LOCATIONS CORRESPONDING TO THE NUMBER OF SUCH GROUPS, A NUMBER OF COMMANDS, A NUMBER OF COMMANDS BITS CORRESPONDING TO THE NUMBER OF GROUPS, AND AN INPUT CONTROL BUFFER TO STORE REQUESTS RECEIVED FROM THE PROCESSING UNIT AND CONTROL CIRCUITS WHICH INCLUDE A DECODER SETTING A PREDETERMINED STATE A DEFINED BIT FROM THE CONTROL DIRECTORY WHEN THE DIRECTORY OF DATA INDICATES THAT THE REQUESTED WORD IS NOT IN THE ANTEMEMORY. APPLICATION TO MICROPROGRAMS TREATMENT SYSTEMS.

FR7832892A 1977-11-22 1978-11-22 DATASHEET DATA PROCESSING SYSTEM Expired FR2425110B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US85394477A 1977-11-22 1977-11-22
US05/853,982 US4156906A (en) 1977-11-22 1977-11-22 Buffer store including control apparatus which facilitates the concurrent processing of a plurality of commands

Publications (2)

Publication Number Publication Date
FR2425110A1 true FR2425110A1 (en) 1979-11-30
FR2425110B1 FR2425110B1 (en) 1986-04-11

Family

ID=27127201

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7832892A Expired FR2425110B1 (en) 1977-11-22 1978-11-22 DATASHEET DATA PROCESSING SYSTEM

Country Status (3)

Country Link
DE (1) DE2849448A1 (en)
FR (1) FR2425110B1 (en)
GB (2) GB2008817B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2447077A1 (en) * 1978-12-11 1980-08-14 Honeywell Inf Systems ANTEMEMORY UNIT WITH ORDER WAITING DEVICE
EP0097790A3 (en) * 1982-06-30 1986-11-20 International Business Machines Corporation Apparatus and method for controlling storage access in a multilevel storage system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611315A (en) * 1968-10-09 1971-10-05 Hitachi Ltd Memory control system for controlling a buffer memory
FR2151425A5 (en) * 1971-08-25 1973-04-13 Ibm
US4056844A (en) * 1974-02-26 1977-11-01 Hitachi, Ltd. Memory control system using plural buffer address arrays

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR111574A (en) * 1973-12-13 1900-01-01

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611315A (en) * 1968-10-09 1971-10-05 Hitachi Ltd Memory control system for controlling a buffer memory
FR2151425A5 (en) * 1971-08-25 1973-04-13 Ibm
US4056844A (en) * 1974-02-26 1977-11-01 Hitachi, Ltd. Memory control system using plural buffer address arrays

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2447077A1 (en) * 1978-12-11 1980-08-14 Honeywell Inf Systems ANTEMEMORY UNIT WITH ORDER WAITING DEVICE
EP0097790A3 (en) * 1982-06-30 1986-11-20 International Business Machines Corporation Apparatus and method for controlling storage access in a multilevel storage system

Also Published As

Publication number Publication date
FR2425110B1 (en) 1986-04-11
DE2849448A1 (en) 1979-06-07
GB2080989A (en) 1982-02-10
GB2008817B (en) 1982-11-10
GB2008817A (en) 1979-06-06
GB2080989B (en) 1982-12-08

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Legal Events

Date Code Title Description
ST Notification of lapse