FR2623332B1 - Circuit integre cmos et procede de fabrication - Google Patents

Circuit integre cmos et procede de fabrication

Info

Publication number
FR2623332B1
FR2623332B1 FR8814117A FR8814117A FR2623332B1 FR 2623332 B1 FR2623332 B1 FR 2623332B1 FR 8814117 A FR8814117 A FR 8814117A FR 8814117 A FR8814117 A FR 8814117A FR 2623332 B1 FR2623332 B1 FR 2623332B1
Authority
FR
France
Prior art keywords
manufacturing
integrated circuit
cmos integrated
cmos
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR8814117A
Other languages
English (en)
Other versions
FR2623332A1 (fr
Inventor
Baird Stuart Lynn
Hunter Bruce Dwight
Kashkooli Fred
Mostyn Graham Yorke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intersil Corp
Original Assignee
Intersil Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intersil Inc filed Critical Intersil Inc
Publication of FR2623332A1 publication Critical patent/FR2623332A1/fr
Application granted granted Critical
Publication of FR2623332B1 publication Critical patent/FR2623332B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00Gettering within semiconductor bodies
    • H10P36/20Intrinsic gettering, i.e. thermally inducing defects by using oxygen present in the silicon body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • H10D84/854Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00Gettering within semiconductor bodies
    • H10P36/03Gettering within semiconductor bodies within silicon bodies
FR8814117A 1987-11-18 1988-10-28 Circuit integre cmos et procede de fabrication Expired - Fee Related FR2623332B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12213087A 1987-11-18 1987-11-18

Publications (2)

Publication Number Publication Date
FR2623332A1 FR2623332A1 (fr) 1989-05-19
FR2623332B1 true FR2623332B1 (fr) 1994-09-23

Family

ID=22400831

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8814117A Expired - Fee Related FR2623332B1 (fr) 1987-11-18 1988-10-28 Circuit integre cmos et procede de fabrication

Country Status (4)

Country Link
JP (1) JPH01161756A (fr)
DE (1) DE3837270A1 (fr)
FR (1) FR2623332B1 (fr)
GB (1) GB2212660B (fr)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5671928A (en) * 1979-11-16 1981-06-15 Chiyou Lsi Gijutsu Kenkyu Kumiai Treatment for silicon substrate
JPS5788736A (en) * 1980-11-21 1982-06-02 Toshiba Corp Preparation of semiconductor device
JPS586140A (ja) * 1981-07-03 1983-01-13 Nec Corp シリコンウエ−ハの製造方法
JPH0612801B2 (ja) * 1981-08-25 1994-02-16 三菱電機株式会社 半導体装置およびその製造方法
US4548654A (en) * 1983-06-03 1985-10-22 Motorola, Inc. Surface denuding of silicon wafer
JPS60133734A (ja) * 1983-12-21 1985-07-16 Mitsubishi Electric Corp 半導体装置の製造方法
JPS60148127A (ja) * 1984-01-13 1985-08-05 Nec Corp 半導体基板の製造方法

Also Published As

Publication number Publication date
FR2623332A1 (fr) 1989-05-19
DE3837270A1 (de) 1989-06-01
GB2212660B (en) 1991-02-13
GB2212660A (en) 1989-07-26
GB8826919D0 (en) 1988-12-21
JPH01161756A (ja) 1989-06-26

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Legal Events

Date Code Title Description
ST Notification of lapse