FR2736207B1 - Procede perfectionne de fabrication de circuits integres - Google Patents

Procede perfectionne de fabrication de circuits integres

Info

Publication number
FR2736207B1
FR2736207B1 FR9507905A FR9507905A FR2736207B1 FR 2736207 B1 FR2736207 B1 FR 2736207B1 FR 9507905 A FR9507905 A FR 9507905A FR 9507905 A FR9507905 A FR 9507905A FR 2736207 B1 FR2736207 B1 FR 2736207B1
Authority
FR
France
Prior art keywords
integrated circuits
improved process
manufacturing integrated
manufacturing
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9507905A
Other languages
English (en)
Other versions
FR2736207A1 (fr
Inventor
Juergen Foerstner
Myriam Combes
Blavier Arlette Marty
Guy Hautekiet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Freescale Semiconducteurs France SAS
Original Assignee
Motorola Semiconducteurs SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Semiconducteurs SA filed Critical Motorola Semiconducteurs SA
Priority to FR9507905A priority Critical patent/FR2736207B1/fr
Priority to EP96109954A priority patent/EP0751558A1/fr
Priority to US08/668,655 priority patent/US5691224A/en
Priority to JP8212214A priority patent/JPH0927562A/ja
Publication of FR2736207A1 publication Critical patent/FR2736207A1/fr
Application granted granted Critical
Publication of FR2736207B1 publication Critical patent/FR2736207B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H10W15/01—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/009—Bi-MOS
FR9507905A 1995-06-30 1995-06-30 Procede perfectionne de fabrication de circuits integres Expired - Fee Related FR2736207B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR9507905A FR2736207B1 (fr) 1995-06-30 1995-06-30 Procede perfectionne de fabrication de circuits integres
EP96109954A EP0751558A1 (fr) 1995-06-30 1996-06-20 Procédé de fabrication de circuits intégrés
US08/668,655 US5691224A (en) 1995-06-30 1996-06-25 Method of making BiCMOS circuit
JP8212214A JPH0927562A (ja) 1995-06-30 1996-07-01 集積回路の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9507905A FR2736207B1 (fr) 1995-06-30 1995-06-30 Procede perfectionne de fabrication de circuits integres

Publications (2)

Publication Number Publication Date
FR2736207A1 FR2736207A1 (fr) 1997-01-03
FR2736207B1 true FR2736207B1 (fr) 1997-09-19

Family

ID=9480572

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9507905A Expired - Fee Related FR2736207B1 (fr) 1995-06-30 1995-06-30 Procede perfectionne de fabrication de circuits integres

Country Status (4)

Country Link
US (1) US5691224A (fr)
EP (1) EP0751558A1 (fr)
JP (1) JPH0927562A (fr)
FR (1) FR2736207B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6831346B1 (en) 2001-05-04 2004-12-14 Cypress Semiconductor Corp. Buried layer substrate isolation in integrated circuits
WO2009029900A1 (fr) * 2007-08-31 2009-03-05 Applied Materials, Inc. Procédés améliorés de formation d'émetteur dans des cellules solaires

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0271526A (ja) * 1988-07-07 1990-03-12 Matsushita Electric Ind Co Ltd 半導体集積回路およびその製造方法
JPH0629079B2 (ja) * 1988-07-18 1994-04-20 株式会社小松製作所 液状物質を封入した連続帯状包装体の加熱・冷却併用式処理方法及び装置
JPH02137262A (ja) * 1988-11-17 1990-05-25 Sanyo Electric Co Ltd 半導体集積回路およびその製造方法
JP3126766B2 (ja) * 1990-12-07 2001-01-22 三菱電機株式会社 半導体装置およびその製造方法
US5406106A (en) * 1992-06-24 1995-04-11 Matsushita Electric Industrial Co., Ltd. Semiconductor Bi-MIS device and method of manufacturing the same

Also Published As

Publication number Publication date
EP0751558A1 (fr) 1997-01-02
FR2736207A1 (fr) 1997-01-03
JPH0927562A (ja) 1997-01-28
US5691224A (en) 1997-11-25

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Legal Events

Date Code Title Description
ST Notification of lapse