FR2805394B1 - Dispositif a semiconducteur et procede de fabrication - Google Patents

Dispositif a semiconducteur et procede de fabrication

Info

Publication number
FR2805394B1
FR2805394B1 FR0013219A FR0013219A FR2805394B1 FR 2805394 B1 FR2805394 B1 FR 2805394B1 FR 0013219 A FR0013219 A FR 0013219A FR 0013219 A FR0013219 A FR 0013219A FR 2805394 B1 FR2805394 B1 FR 2805394B1
Authority
FR
France
Prior art keywords
manufacture
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0013219A
Other languages
English (en)
Other versions
FR2805394A1 (fr
Inventor
Toshiaki Iwamatsu
Takashi Ipposhi
Takuji Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of FR2805394A1 publication Critical patent/FR2805394A1/fr
Application granted granted Critical
Publication of FR2805394B1 publication Critical patent/FR2805394B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
FR0013219A 2000-02-17 2000-10-16 Dispositif a semiconducteur et procede de fabrication Expired - Lifetime FR2805394B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000039484A JP2001230315A (ja) 2000-02-17 2000-02-17 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
FR2805394A1 FR2805394A1 (fr) 2001-08-24
FR2805394B1 true FR2805394B1 (fr) 2005-03-04

Family

ID=18563040

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0013219A Expired - Lifetime FR2805394B1 (fr) 2000-02-17 2000-10-16 Dispositif a semiconducteur et procede de fabrication

Country Status (7)

Country Link
US (3) US6495898B1 (fr)
JP (1) JP2001230315A (fr)
KR (1) KR100376238B1 (fr)
CN (1) CN1187811C (fr)
DE (1) DE10051579B4 (fr)
FR (1) FR2805394B1 (fr)
TW (1) TW462077B (fr)

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JP2002208705A (ja) * 2001-01-09 2002-07-26 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2002270846A (ja) * 2001-03-12 2002-09-20 Oki Electric Ind Co Ltd 半導体装置の製造方法
US6667224B1 (en) * 2001-08-13 2003-12-23 Cypress Semiconductor Corp. Method to eliminate inverse narrow width effect in small geometry MOS transistors
US6716740B2 (en) * 2001-10-09 2004-04-06 Taiwan Semiconductor Manufacturing Co., Ltd. Method for depositing silicon oxide incorporating an outgassing step
US20030107078A1 (en) * 2001-12-07 2003-06-12 Winbond Electronics Corporation Self-aligned dual-floating gate memory cell .
JP4139105B2 (ja) 2001-12-20 2008-08-27 株式会社ルネサステクノロジ 半導体装置の製造方法
JP2003243662A (ja) * 2002-02-14 2003-08-29 Mitsubishi Electric Corp 半導体装置およびその製造方法、半導体ウェハ
US20030194871A1 (en) * 2002-04-15 2003-10-16 Macronix International Co., Ltd. Method of stress and damage elimination during formation of isolation device
JP4579512B2 (ja) 2003-07-15 2010-11-10 セイコーエプソン株式会社 半導体装置およびその製造方法
JP2005183686A (ja) * 2003-12-19 2005-07-07 Renesas Technology Corp 半導体装置およびその製造方法
KR100545182B1 (ko) * 2003-12-31 2006-01-24 동부아남반도체 주식회사 반도체 소자 및 그의 제조 방법
US7129559B2 (en) * 2004-04-09 2006-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. High voltage semiconductor device utilizing a deep trench structure
JP4745620B2 (ja) * 2004-04-20 2011-08-10 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP4811901B2 (ja) 2004-06-03 2011-11-09 ルネサスエレクトロニクス株式会社 半導体装置
US7233201B2 (en) * 2004-08-31 2007-06-19 Micron Technology, Inc. Single-ended pseudo-differential output driver
US20060094171A1 (en) * 2004-11-04 2006-05-04 Taiwan Semiconductor Manufacturing Co., Ltd. Isolation trench thermal annealing method for non-bulk silicon semiconductor substrate
JP2006319164A (ja) * 2005-05-13 2006-11-24 Renesas Technology Corp 半導体装置の製造方法
KR100677998B1 (ko) * 2005-09-30 2007-02-02 동부일렉트로닉스 주식회사 반도체 소자의 셸로우 트렌치 소자분리막 제조 방법
JP4894245B2 (ja) * 2005-11-29 2012-03-14 セイコーエプソン株式会社 半導体装置の製造方法
TWI300593B (en) * 2006-02-07 2008-09-01 Touch Micro System Tech Method of segmenting wafer
US7732287B2 (en) * 2006-05-02 2010-06-08 Honeywell International Inc. Method of forming a body-tie
US7442601B2 (en) * 2006-09-18 2008-10-28 Advanced Micro Devices, Inc. Stress enhanced CMOS circuits and methods for their fabrication
JP5137378B2 (ja) * 2006-10-20 2013-02-06 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP5071652B2 (ja) * 2007-11-02 2012-11-14 セイコーエプソン株式会社 半導体装置
US7964897B2 (en) * 2008-07-22 2011-06-21 Honeywell International Inc. Direct contact to area efficient body tie process flow
US8680617B2 (en) * 2009-10-06 2014-03-25 International Business Machines Corporation Split level shallow trench isolation for area efficient body contacts in SOI MOSFETS
US20110115019A1 (en) * 2009-11-13 2011-05-19 Maxim Integrated Products, Inc. Cmos compatible low gate charge lateral mosfet
US8946851B1 (en) 2009-11-13 2015-02-03 Maxim Integrated Products, Inc. Integrated MOS power transistor with thin gate oxide and low gate charge
US8963241B1 (en) 2009-11-13 2015-02-24 Maxim Integrated Products, Inc. Integrated MOS power transistor with poly field plate extension for depletion assist
US8969958B1 (en) 2009-11-13 2015-03-03 Maxim Integrated Products, Inc. Integrated MOS power transistor with body extension region for poly field plate depletion assist
US20110115018A1 (en) * 2009-11-13 2011-05-19 Maxim Integrated Products, Inc. Mos power transistor
US8987818B1 (en) 2009-11-13 2015-03-24 Maxim Integrated Products, Inc. Integrated MOS power transistor with thin gate oxide and low gate charge
US10672748B1 (en) 2010-06-02 2020-06-02 Maxim Integrated Products, Inc. Use of device assembly for a generalization of three-dimensional heterogeneous technologies integration
US8349653B2 (en) 2010-06-02 2013-01-08 Maxim Integrated Products, Inc. Use of device assembly for a generalization of three-dimensional metal interconnect technologies
JP5959350B2 (ja) * 2012-07-19 2016-08-02 三菱電機株式会社 半導体装置の製造方法
US10163679B1 (en) 2017-05-31 2018-12-25 Globalfoundries Inc. Shallow trench isolation formation without planarization
CN113394160B (zh) * 2021-05-14 2023-04-04 上海华力集成电路制造有限公司 半导体器件的制作方法

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JPS60244037A (ja) * 1984-05-17 1985-12-03 Toshiba Corp 半導体装置及びその製造方法
FR2610140B1 (fr) * 1987-01-26 1990-04-20 Commissariat Energie Atomique Circuit integre cmos et procede de fabrication de ses zones d'isolation electrique
JPH01122158A (ja) 1987-11-05 1989-05-15 Mitsubishi Electric Corp 半導体装置
FR2631488B1 (fr) * 1988-05-10 1990-07-27 Thomson Hybrides Microondes Circuit integre hyperfrequence de type planar, comportant au moins un composant mesa, et son procede de fabrication
US5240512A (en) * 1990-06-01 1993-08-31 Texas Instruments Incorporated Method and structure for forming a trench within a semiconductor layer of material
US5145802A (en) * 1991-11-12 1992-09-08 United Technologies Corporation Method of making SOI circuit with buried connectors
JPH0834261B2 (ja) * 1992-06-17 1996-03-29 インターナショナル・ビジネス・マシーンズ・コーポレイション Ｂｉｃｍｏｓ集積回路用のｓｏｉ構造体およびその製造方法
US5399507A (en) * 1994-06-27 1995-03-21 Motorola, Inc. Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications
KR0147630B1 (ko) * 1995-04-21 1998-11-02 김광호 반도체 장치의 소자분리방법
US5780352A (en) * 1995-10-23 1998-07-14 Motorola, Inc. Method of forming an isolation oxide for silicon-on-insulator technology
KR100214068B1 (ko) * 1995-11-21 1999-08-02 김영환 반도체 장치의 소자분리막 형성방법
KR100233286B1 (ko) * 1996-06-29 1999-12-01 김영환 반도체 장치 및 그 제조방법
US5858842A (en) * 1996-07-03 1999-01-12 Samsung Electronics Co., Ltd. Methods of forming combined trench and locos-based electrical isolation regions in semiconductor substrates
JP3602679B2 (ja) * 1997-02-26 2004-12-15 株式会社ルネサステクノロジ 半導体装置およびその製造方法
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JP3061020B2 (ja) 1997-11-12 2000-07-10 日本電気株式会社 誘電体分離型半導体装置
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Also Published As

Publication number Publication date
KR100376238B1 (ko) 2003-03-15
JP2001230315A (ja) 2001-08-24
DE10051579A1 (de) 2001-09-06
FR2805394A1 (fr) 2001-08-24
TW462077B (en) 2001-11-01
KR20010081943A (ko) 2001-08-29
US20020100939A1 (en) 2002-08-01
US6495898B1 (en) 2002-12-17
US6627512B2 (en) 2003-09-30
US20020123205A1 (en) 2002-09-05
DE10051579B4 (de) 2005-11-10
CN1309423A (zh) 2001-08-22
CN1187811C (zh) 2005-02-02

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Legal Events

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TP Transmission of property
PLFP Fee payment

Year of fee payment: 16

CA Change of address

Effective date: 20160217

TP Transmission of property

Owner name: RENESAS ELECTRONICS CORPORATION, JP

Effective date: 20160217

PLFP Fee payment

Year of fee payment: 17

PLFP Fee payment

Year of fee payment: 18