FR2819629B1 - Circuit integre a risque de percage reduit entre des couches enterrees, et procede de fabrication - Google Patents

Circuit integre a risque de percage reduit entre des couches enterrees, et procede de fabrication

Info

Publication number
FR2819629B1
FR2819629B1 FR0100412A FR0100412A FR2819629B1 FR 2819629 B1 FR2819629 B1 FR 2819629B1 FR 0100412 A FR0100412 A FR 0100412A FR 0100412 A FR0100412 A FR 0100412A FR 2819629 B1 FR2819629 B1 FR 2819629B1
Authority
FR
France
Prior art keywords
integrated circuit
manufacturing process
buried layers
risk
reduced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0100412A
Other languages
English (en)
Other versions
FR2819629A1 (fr
Inventor
Olivier Menut
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0100412A priority Critical patent/FR2819629B1/fr
Priority to JP2002556931A priority patent/JP2004527102A/ja
Priority to EP02710091A priority patent/EP1352420A1/fr
Priority to US10/250,538 priority patent/US6812541B2/en
Priority to PCT/FR2002/000055 priority patent/WO2002056363A1/fr
Publication of FR2819629A1 publication Critical patent/FR2819629A1/fr
Application granted granted Critical
Publication of FR2819629B1 publication Critical patent/FR2819629B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
FR0100412A 2001-01-12 2001-01-12 Circuit integre a risque de percage reduit entre des couches enterrees, et procede de fabrication Expired - Fee Related FR2819629B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR0100412A FR2819629B1 (fr) 2001-01-12 2001-01-12 Circuit integre a risque de percage reduit entre des couches enterrees, et procede de fabrication
JP2002556931A JP2004527102A (ja) 2001-01-12 2002-01-09 半導体基板を備える集積回路
EP02710091A EP1352420A1 (fr) 2001-01-12 2002-01-09 Structure d isolation de couches enterrees par tranchees enterrees, et procede de fabrication
US10/250,538 US6812541B2 (en) 2001-01-12 2002-01-09 Integrated circuit with a reduced risk of punch-through between buried layers, and fabrication process
PCT/FR2002/000055 WO2002056363A1 (fr) 2001-01-12 2002-01-09 Structure d isolation de couches enterrees par tranchees enterrees, et procede de fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0100412A FR2819629B1 (fr) 2001-01-12 2001-01-12 Circuit integre a risque de percage reduit entre des couches enterrees, et procede de fabrication

Publications (2)

Publication Number Publication Date
FR2819629A1 FR2819629A1 (fr) 2002-07-19
FR2819629B1 true FR2819629B1 (fr) 2003-07-04

Family

ID=8858763

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0100412A Expired - Fee Related FR2819629B1 (fr) 2001-01-12 2001-01-12 Circuit integre a risque de percage reduit entre des couches enterrees, et procede de fabrication

Country Status (5)

Country Link
US (1) US6812541B2 (fr)
EP (1) EP1352420A1 (fr)
JP (1) JP2004527102A (fr)
FR (1) FR2819629B1 (fr)
WO (1) WO2002056363A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4182986B2 (ja) * 2006-04-19 2008-11-19 トヨタ自動車株式会社 半導体装置とその製造方法
US9293357B2 (en) * 2012-07-02 2016-03-22 Texas Instruments Incorporated Sinker with a reduced width

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900005124B1 (ko) * 1984-10-17 1990-07-19 가부시기가이샤 히다찌세이사꾸쇼 상보형 반도체장치
US4885618A (en) * 1986-03-24 1989-12-05 General Motors Corporation Insulated gate FET having a buried insulating barrier
US4829359A (en) * 1987-05-29 1989-05-09 Harris Corp. CMOS device having reduced spacing between N and P channel
JPS63312669A (ja) * 1987-06-16 1988-12-21 Mitsubishi Electric Corp 固体撮像素子
EP0398468A3 (fr) * 1989-05-16 1991-03-13 Kabushiki Kaisha Toshiba Substrat isolé diélectriquement et dispositif semi-conducteur utilisant ce substrat
JPH0945904A (ja) * 1995-07-28 1997-02-14 Matsushita Electron Corp 半導体装置およびその製造方法
US6246094B1 (en) * 1998-10-20 2001-06-12 Winbond Electronics Corporation Buried shallow trench isolation and method for forming the same
JP2000332098A (ja) * 1999-05-18 2000-11-30 Hitachi Ltd 半導体集積回路装置およびその製造方法

Also Published As

Publication number Publication date
JP2004527102A (ja) 2004-09-02
EP1352420A1 (fr) 2003-10-15
FR2819629A1 (fr) 2002-07-19
WO2002056363A1 (fr) 2002-07-18
US6812541B2 (en) 2004-11-02
US20040075107A1 (en) 2004-04-22

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Legal Events

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