FR2847076A1 - Procede de detachement d'une couche mince a temperature moderee apres co-implantation - Google Patents

Procede de detachement d'une couche mince a temperature moderee apres co-implantation

Info

Publication number
FR2847076A1
FR2847076A1 FR0213935A FR0213935A FR2847076A1 FR 2847076 A1 FR2847076 A1 FR 2847076A1 FR 0213935 A FR0213935 A FR 0213935A FR 0213935 A FR0213935 A FR 0213935A FR 2847076 A1 FR2847076 A1 FR 2847076A1
Authority
FR
France
Prior art keywords
detaching
implantation
thin layer
detachment
defects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR0213935A
Other languages
English (en)
Other versions
FR2847076B1 (fr
Inventor
Ian Cayrefourcq
Mohamed Nadia Ben
Blanchard Christelle Lagahe
Nguyet Phuong Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0213935A priority Critical patent/FR2847076B1/fr
Application filed by Commissariat a lEnergie Atomique CEA, Soitec SA filed Critical Commissariat a lEnergie Atomique CEA
Priority to CN2003801023000A priority patent/CN1708843B/zh
Priority to PCT/EP2003/013148 priority patent/WO2004042779A2/fr
Priority to KR1020057008067A priority patent/KR101122859B1/ko
Priority to JP2004549162A priority patent/JP4999272B2/ja
Priority to EP03795839.4A priority patent/EP1559139B1/fr
Priority to AU2003298137A priority patent/AU2003298137A1/en
Priority to TW092130723A priority patent/TWI294663B/zh
Publication of FR2847076A1 publication Critical patent/FR2847076A1/fr
Application granted granted Critical
Publication of FR2847076B1 publication Critical patent/FR2847076B1/fr
Priority to JP2011242033A priority patent/JP2012084897A/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

Un procédé de détachement d'une couche mince d'un substrat source comporte les étapes suivantes:• implantation d'ions ou d'espèces gazeuses dans le substrat source de façon à y former une zone enterrée fragilisée par la présence de défauts;• fracture dans la zone fragilisée menant au détachement de la couche mince d'avec le substrat source.Deux espèces sont implantées dont l'une est apte à former des défauts et l'autre est apte à occuper ces défauts, le détachement étant effectué à une température inférieure à celle pour laquelle un détachement pourrait être obtenu avec la seule dose de la première espèce.
FR0213935A 2002-11-07 2002-11-07 Procede de detachement d'une couche mince a temperature moderee apres co-implantation Expired - Fee Related FR2847076B1 (fr)

Priority Applications (9)

Application Number Priority Date Filing Date Title
FR0213935A FR2847076B1 (fr) 2002-11-07 2002-11-07 Procede de detachement d'une couche mince a temperature moderee apres co-implantation
PCT/EP2003/013148 WO2004042779A2 (fr) 2002-11-07 2003-10-30 Procede de separation d'une couche mince a une temperature moyenne apres implantation conjointe
KR1020057008067A KR101122859B1 (ko) 2002-11-07 2003-10-30 공동?주입후 온화한 온도에서 박막의 박리 방법
JP2004549162A JP4999272B2 (ja) 2002-11-07 2003-10-30 共注入後に中温で薄膜を分離する方法
CN2003801023000A CN1708843B (zh) 2002-11-07 2003-10-30 在共注入后在中等温度下分离薄膜的方法
EP03795839.4A EP1559139B1 (fr) 2002-11-07 2003-10-30 Procede de separation d'une couche mince a une temperature moyenne apres implantation conjointe
AU2003298137A AU2003298137A1 (en) 2002-11-07 2003-10-30 Method of detaching a thin film at moderate temperature after co-implantation
TW092130723A TWI294663B (en) 2002-11-07 2003-11-04 Method of detaching a thin film at moderate temperature after co-implantation
JP2011242033A JP2012084897A (ja) 2002-11-07 2011-11-04 共注入後に中温で薄膜を分離する方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0213935A FR2847076B1 (fr) 2002-11-07 2002-11-07 Procede de detachement d'une couche mince a temperature moderee apres co-implantation

Publications (2)

Publication Number Publication Date
FR2847076A1 true FR2847076A1 (fr) 2004-05-14
FR2847076B1 FR2847076B1 (fr) 2005-02-18

Family

ID=32116442

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0213935A Expired - Fee Related FR2847076B1 (fr) 2002-11-07 2002-11-07 Procede de detachement d'une couche mince a temperature moderee apres co-implantation

Country Status (8)

Country Link
EP (1) EP1559139B1 (fr)
JP (2) JP4999272B2 (fr)
KR (1) KR101122859B1 (fr)
CN (1) CN1708843B (fr)
AU (1) AU2003298137A1 (fr)
FR (1) FR2847076B1 (fr)
TW (1) TWI294663B (fr)
WO (1) WO2004042779A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2907966A1 (fr) * 2006-10-27 2008-05-02 Soitec Silicon On Insulator Procede de fabrication d'un substrat.
EP2028685A1 (fr) * 2007-08-20 2009-02-25 Siltron Inc. Procédé de fabrication pour substrat SSOI

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
EP1605504B1 (fr) * 2004-06-10 2011-05-25 S.O.I. Tec Silicon on Insulator Technologies S.A. Procédé pour la fabrication d'une tranche SOI
CN100527416C (zh) * 2004-08-18 2009-08-12 康宁股份有限公司 应变绝缘体上半导体结构以及应变绝缘体上半导体结构的制造方法
CN101027768B (zh) * 2004-09-21 2010-11-03 S.O.I.Tec绝缘体上硅技术公司 根据避免气泡形成和限制粗糙度的条件来进行共注入步骤的薄层转移方法
DE602004027422D1 (de) * 2004-09-21 2010-07-08 Soitec Silicon On Insulator Übertragungsverfahren mit einer behandlung einer zu verbindenden oberfläche
WO2006037783A1 (fr) * 2004-10-04 2006-04-13 S.O.I.Tec Silicon On Insulator Technologies Procédé de transfert d'une couche mince comprenant une perturbation controlée d'une structure cristalline
FR2889887B1 (fr) 2005-08-16 2007-11-09 Commissariat Energie Atomique Procede de report d'une couche mince sur un support
FR2891281B1 (fr) 2005-09-28 2007-12-28 Commissariat Energie Atomique Procede de fabrication d'un element en couches minces.
FR2910179B1 (fr) 2006-12-19 2009-03-13 Commissariat Energie Atomique PROCEDE DE FABRICATION DE COUCHES MINCES DE GaN PAR IMPLANTATION ET RECYCLAGE D'UN SUBSTRAT DE DEPART
FR2947098A1 (fr) 2009-06-18 2010-12-24 Commissariat Energie Atomique Procede de transfert d'une couche mince sur un substrat cible ayant un coefficient de dilatation thermique different de celui de la couche mince
FR2949606B1 (fr) 2009-08-26 2011-10-28 Commissariat Energie Atomique Procede de detachement par fracture d'un film mince de silicium mettant en oeuvre une triple implantation
FR2974944B1 (fr) * 2011-05-02 2013-06-14 Commissariat Energie Atomique Procédé de formation d'une fracture dans un matériau
KR101219358B1 (ko) * 2011-07-26 2013-01-21 삼성코닝정밀소재 주식회사 기판 분리 방법 및 이를 이용한 접합기판 제조방법
FR3045678B1 (fr) 2015-12-22 2017-12-22 Soitec Silicon On Insulator Procede de fabrication d'une couche piezoelectrique monocristalline et dispositif microelectronique, photonique ou optique comprenant une telle couche
FR3045677B1 (fr) 2015-12-22 2019-07-19 Soitec Procede de fabrication d'une couche monocristalline, notamment piezoelectrique
JP6563360B2 (ja) * 2016-04-05 2019-08-21 信越化学工業株式会社 酸化物単結晶薄膜を備えた複合ウェーハの製造方法
CN106222754A (zh) * 2016-07-29 2016-12-14 成都立威讯科技有限公司 一种工艺精湛的蓝宝石分离方法
DE102016118268B4 (de) * 2016-09-27 2025-06-26 Infineon Technologies Ag Verfahren zum Bearbeiten eines einkristallinen Substrats und mikromechanische Struktur
WO2020247531A1 (fr) * 2019-06-06 2020-12-10 Applied Materials, Inc. Procédés de post-traitement de films diélectriques à base de nitrure de silicium à l'aide d'un plasma à faible dose d'énergie
FR3108440B1 (fr) * 2020-03-23 2025-01-17 Soitec Silicon On Insulator Procédé de préparation d’une couche mince

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020025604A1 (en) * 2000-08-30 2002-02-28 Sandip Tiwari Low temperature semiconductor layering and three-dimensional electronic circuits using the layering
US20020153563A1 (en) * 1998-04-17 2002-10-24 Atsushi Ogura Silicon-on-insulator(soi)substrate

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2738671B1 (fr) * 1995-09-13 1997-10-10 Commissariat Energie Atomique Procede de fabrication de films minces a materiau semiconducteur
US5877070A (en) 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US6150239A (en) * 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
JP3412470B2 (ja) * 1997-09-04 2003-06-03 三菱住友シリコン株式会社 Ｓｏｉ基板の製造方法
FR2811807B1 (fr) * 2000-07-12 2003-07-04 Commissariat Energie Atomique Procede de decoupage d'un bloc de materiau et de formation d'un film mince

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020153563A1 (en) * 1998-04-17 2002-10-24 Atsushi Ogura Silicon-on-insulator(soi)substrate
US20020025604A1 (en) * 2000-08-30 2002-02-28 Sandip Tiwari Low temperature semiconductor layering and three-dimensional electronic circuits using the layering

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
AGARWAL A ET AL: "EFFICIENT PRODUCTION OF SILICON-ON-INSULATOR FILMS BY CO- IMPLANTATION OF HE+ WITH H+", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 72, no. 9, 2 March 1998 (1998-03-02), pages 1086 - 1088, XP000742819, ISSN: 0003-6951 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2907966A1 (fr) * 2006-10-27 2008-05-02 Soitec Silicon On Insulator Procede de fabrication d'un substrat.
US7833877B2 (en) 2006-10-27 2010-11-16 S.O.I.Tec Silicon On Insulator Technologies Method for producing a semiconductor substrate
EP2028685A1 (fr) * 2007-08-20 2009-02-25 Siltron Inc. Procédé de fabrication pour substrat SSOI
US7906408B2 (en) 2007-08-20 2011-03-15 Siltron Inc. Method of manufacturing strained silicon on-insulator substrate

Also Published As

Publication number Publication date
FR2847076B1 (fr) 2005-02-18
JP2006505928A (ja) 2006-02-16
EP1559139A2 (fr) 2005-08-03
KR20050060111A (ko) 2005-06-21
AU2003298137A8 (en) 2004-06-07
AU2003298137A1 (en) 2004-06-07
WO2004042779A3 (fr) 2004-09-23
TW200423295A (en) 2004-11-01
KR101122859B1 (ko) 2012-03-21
JP4999272B2 (ja) 2012-08-15
JP2012084897A (ja) 2012-04-26
TWI294663B (en) 2008-03-11
WO2004042779A2 (fr) 2004-05-21
EP1559139B1 (fr) 2013-05-29
CN1708843B (zh) 2010-08-18
CN1708843A (zh) 2005-12-14

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Legal Events

Date Code Title Description
CD Change of name or company name

Owner name: SOITEC, FR

Effective date: 20120423

Owner name: COMMISSARIAT A L ENERGIE ATOMIQUE, FR

Effective date: 20120423

ST Notification of lapse

Effective date: 20160729