FR2947384B1 - Procede de realisation d'un transistor a source et drain metalliques - Google Patents

Procede de realisation d'un transistor a source et drain metalliques

Info

Publication number
FR2947384B1
FR2947384B1 FR0954350A FR0954350A FR2947384B1 FR 2947384 B1 FR2947384 B1 FR 2947384B1 FR 0954350 A FR0954350 A FR 0954350A FR 0954350 A FR0954350 A FR 0954350A FR 2947384 B1 FR2947384 B1 FR 2947384B1
Authority
FR
France
Prior art keywords
drain
producing
metal source
source transistor
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0954350A
Other languages
English (en)
Other versions
FR2947384A1 (fr
Inventor
Bernard Previtali
Thierry Poiroux
Maud Vinet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat a lEnergie Atomique CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR0954350A priority Critical patent/FR2947384B1/fr
Priority to US12/796,282 priority patent/US8021986B2/en
Publication of FR2947384A1 publication Critical patent/FR2947384A1/fr
Application granted granted Critical
Publication of FR2947384B1 publication Critical patent/FR2947384B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs
    • H10D30/6734—Multi-gate TFTs having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/924—To facilitate selective etching
FR0954350A 2009-06-25 2009-06-25 Procede de realisation d'un transistor a source et drain metalliques Active FR2947384B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0954350A FR2947384B1 (fr) 2009-06-25 2009-06-25 Procede de realisation d'un transistor a source et drain metalliques
US12/796,282 US8021986B2 (en) 2009-06-25 2010-06-08 Method for producing a transistor with metallic source and drain

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0954350A FR2947384B1 (fr) 2009-06-25 2009-06-25 Procede de realisation d'un transistor a source et drain metalliques

Publications (2)

Publication Number Publication Date
FR2947384A1 FR2947384A1 (fr) 2010-12-31
FR2947384B1 true FR2947384B1 (fr) 2012-03-30

Family

ID=41650187

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0954350A Active FR2947384B1 (fr) 2009-06-25 2009-06-25 Procede de realisation d'un transistor a source et drain metalliques

Country Status (2)

Country Link
US (1) US8021986B2 (fr)
FR (1) FR2947384B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2976122A1 (fr) * 2011-05-31 2012-12-07 St Microelectronics Crolles 2 Transistor mosfet, composant incluant plusieurs tels transistors et procede de fabrication
CN106062962A (zh) * 2014-03-21 2016-10-26 英特尔公司 用于集成富Ge的p‑MOS源极/漏极接触部的技术
CN113922812B (zh) * 2021-10-13 2025-01-24 西交利物浦大学 与非门逻辑电路及其制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6080661A (en) * 1998-05-29 2000-06-27 Philips Electronics North America Corp. Methods for fabricating gate and diffusion contacts in self-aligned contact processes
KR100561960B1 (ko) * 2000-04-03 2006-03-21 도요 보세키 가부시키가이샤 공동 함유 폴리에스테르계 필름
FR2810157B1 (fr) * 2000-06-09 2002-08-16 Commissariat Energie Atomique Procede de realisation d'un composant electronique a source, drain et grille auto-allignes, en architecture damascene
US6686247B1 (en) 2002-08-22 2004-02-03 Intel Corporation Self-aligned contacts to gates
GB0316395D0 (en) 2003-07-12 2003-08-13 Hewlett Packard Development Co A transistor device with metallic electrodes and a method for use in forming such a device
EP1650796A3 (fr) * 2004-10-20 2010-12-08 STMicroelectronics (Crolles 2) SAS Procédé de prise de contact sur une région d'un circuit intégré, en particulier sur les électrodes d'un transistor
US7648871B2 (en) * 2005-10-21 2010-01-19 International Business Machines Corporation Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabricating same
FR2893762B1 (fr) 2005-11-18 2007-12-21 Commissariat Energie Atomique Procede de realisation de transistor a double grilles auto-alignees par reduction de motifs de grille
ATE457525T1 (de) * 2005-11-28 2010-02-15 Nxp Bv Verfahren zur herstellung selbstausgerichteter schottky-dioden für halbleiterbauelemente
US7470615B2 (en) * 2006-07-26 2008-12-30 International Business Machines Corporation Semiconductor structure with self-aligned device contacts
FR2915023B1 (fr) * 2007-04-13 2009-07-17 St Microelectronics Crolles 2 Realisation de contacts auto-positionnes par epitaxie
US20090101972A1 (en) * 2007-10-17 2009-04-23 Gaines R Stockton Process for fabricating a field-effect transistor with doping segregation used in source and/or drain

Also Published As

Publication number Publication date
US20110003443A1 (en) 2011-01-06
FR2947384A1 (fr) 2010-12-31
US8021986B2 (en) 2011-09-20

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