FR2967295B1 - Procédé de traitement d'une structure multicouche - Google Patents
Procédé de traitement d'une structure multicoucheInfo
- Publication number
- FR2967295B1 FR2967295B1 FR1059135A FR1059135A FR2967295B1 FR 2967295 B1 FR2967295 B1 FR 2967295B1 FR 1059135 A FR1059135 A FR 1059135A FR 1059135 A FR1059135 A FR 1059135A FR 2967295 B1 FR2967295 B1 FR 2967295B1
- Authority
- FR
- France
- Prior art keywords
- wafer
- chemical etch
- layer
- multilayer structure
- upper layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/60—Wet etching
- H10P50/64—Wet etching of semiconductor materials
- H10P50/642—Chemical etching
- H10P50/644—Anisotropic liquid etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1922—Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Landscapes
- Element Separation (AREA)
- Weting (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1059135A FR2967295B1 (fr) | 2010-11-05 | 2010-11-05 | Procédé de traitement d'une structure multicouche |
| PCT/EP2011/068502 WO2012059350A2 (fr) | 2010-11-05 | 2011-10-24 | Procédé de traitement de structure multicouche |
| TW100140379A TW201232657A (en) | 2010-11-05 | 2011-11-04 | A method of treating a multilayer structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1059135A FR2967295B1 (fr) | 2010-11-05 | 2010-11-05 | Procédé de traitement d'une structure multicouche |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2967295A1 FR2967295A1 (fr) | 2012-05-11 |
| FR2967295B1 true FR2967295B1 (fr) | 2013-01-11 |
Family
ID=44167962
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR1059135A Expired - Fee Related FR2967295B1 (fr) | 2010-11-05 | 2010-11-05 | Procédé de traitement d'une structure multicouche |
Country Status (3)
| Country | Link |
|---|---|
| FR (1) | FR2967295B1 (fr) |
| TW (1) | TW201232657A (fr) |
| WO (1) | WO2012059350A2 (fr) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3003997B1 (fr) | 2013-03-29 | 2015-03-20 | Soitec Silicon On Insulator | Procede de fabrication d'une structure composite |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0917984A (ja) * | 1995-06-29 | 1997-01-17 | Sumitomo Sitix Corp | 貼り合わせｓｏｉ基板の製造方法 |
| FR2880184B1 (fr) * | 2004-12-28 | 2007-03-30 | Commissariat Energie Atomique | Procede de detourage d'une structure obtenue par assemblage de deux plaques |
| FR2935535B1 (fr) * | 2008-09-02 | 2010-12-10 | S O I Tec Silicon On Insulator Tech | Procede de detourage mixte. |
-
2010
- 2010-11-05 FR FR1059135A patent/FR2967295B1/fr not_active Expired - Fee Related
-
2011
- 2011-10-24 WO PCT/EP2011/068502 patent/WO2012059350A2/fr not_active Ceased
- 2011-11-04 TW TW100140379A patent/TW201232657A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2012059350A2 (fr) | 2012-05-10 |
| FR2967295A1 (fr) | 2012-05-11 |
| WO2012059350A3 (fr) | 2012-11-22 |
| TW201232657A (en) | 2012-08-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| CD | Change of name or company name |
Owner name: SOITEC, FR Effective date: 20120907 |
|
| ST | Notification of lapse |
Effective date: 20140731 |