FR2980657B1 - Circuit electronique presentant une desynchronisation materielle au sein d'une periode d'horloge - Google Patents
Circuit electronique presentant une desynchronisation materielle au sein d'une periode d'horlogeInfo
- Publication number
- FR2980657B1 FR2980657B1 FR1158692A FR1158692A FR2980657B1 FR 2980657 B1 FR2980657 B1 FR 2980657B1 FR 1158692 A FR1158692 A FR 1158692A FR 1158692 A FR1158692 A FR 1158692A FR 2980657 B1 FR2980657 B1 FR 2980657B1
- Authority
- FR
- France
- Prior art keywords
- desynchronization
- electronic circuit
- clock period
- clock
- period
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/002—Countermeasures against attacks on cryptographic mechanisms
- H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Theoretical Computer Science (AREA)
- Electronic Switches (AREA)
- Microcomputers (AREA)
- Manipulation Of Pulses (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1158692A FR2980657B1 (fr) | 2011-09-28 | 2011-09-28 | Circuit electronique presentant une desynchronisation materielle au sein d'une periode d'horloge |
| TW101135405A TWI562591B (en) | 2011-09-28 | 2012-09-26 | Electronic circuit presenting hardware desynchronisation within a clock period |
| KR1020120107843A KR102027001B1 (ko) | 2011-09-28 | 2012-09-27 | 한 클럭 주기 내의 하드웨어 디싱크로니세이션을 나타내는 전자 회로 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1158692A FR2980657B1 (fr) | 2011-09-28 | 2011-09-28 | Circuit electronique presentant une desynchronisation materielle au sein d'une periode d'horloge |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2980657A1 FR2980657A1 (fr) | 2013-03-29 |
| FR2980657B1 true FR2980657B1 (fr) | 2014-06-20 |
Family
ID=45496051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR1158692A Active FR2980657B1 (fr) | 2011-09-28 | 2011-09-28 | Circuit electronique presentant une desynchronisation materielle au sein d'une periode d'horloge |
Country Status (3)
| Country | Link |
|---|---|
| KR (1) | KR102027001B1 (fr) |
| FR (1) | FR2980657B1 (fr) |
| TW (1) | TWI562591B (fr) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10891396B2 (en) * | 2016-05-27 | 2021-01-12 | Samsung Electronics Co., Ltd. | Electronic circuit performing encryption/decryption operation to prevent side- channel analysis attack, and electronic device including the same |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5404402A (en) * | 1993-12-21 | 1995-04-04 | Gi Corporation | Clock frequency modulation for secure microprocessors |
| JPH07297720A (ja) * | 1994-04-25 | 1995-11-10 | Hitachi Ltd | コンパレータ |
| US5923613A (en) * | 1998-03-18 | 1999-07-13 | Etron Technology, Inc. | Latched type clock synchronizer with additional 180°-phase shift clock |
| US7554865B2 (en) * | 2006-09-21 | 2009-06-30 | Atmel Corporation | Randomizing current consumption in memory devices |
| US7423928B2 (en) * | 2007-01-30 | 2008-09-09 | Atmel Corporation | Clock circuitry for DDR-SDRAM memory controller |
| US7940100B2 (en) * | 2007-09-24 | 2011-05-10 | Qualcomm, Incorporated | Delay circuits matching delays of synchronous circuits |
| FR2932336B1 (fr) * | 2008-06-06 | 2010-06-18 | Tiempo | Circuit asynchrone insensible aux delais avec circuit d'insertion de delai |
| JP5494252B2 (ja) * | 2009-09-11 | 2014-05-14 | ソニー株式会社 | 同期発振器、クロック再生装置、クロック分配回路、およびマルチモード注入回路 |
-
2011
- 2011-09-28 FR FR1158692A patent/FR2980657B1/fr active Active
-
2012
- 2012-09-26 TW TW101135405A patent/TWI562591B/zh active
- 2012-09-27 KR KR1020120107843A patent/KR102027001B1/ko active Active
Also Published As
| Publication number | Publication date |
|---|---|
| KR20130034621A (ko) | 2013-04-05 |
| TW201330576A (zh) | 2013-07-16 |
| FR2980657A1 (fr) | 2013-03-29 |
| KR102027001B1 (ko) | 2019-09-30 |
| TWI562591B (en) | 2016-12-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PLFP | Fee payment |
Year of fee payment: 6 |
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| PLFP | Fee payment |
Year of fee payment: 7 |
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| PLFP | Fee payment |
Year of fee payment: 8 |
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| PLFP | Fee payment |
Year of fee payment: 9 |
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| PLFP | Fee payment |
Year of fee payment: 10 |
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| PLFP | Fee payment |
Year of fee payment: 11 |
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| PLFP | Fee payment |
Year of fee payment: 12 |
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| CA | Change of address |
Effective date: 20230206 |
|
| CD | Change of name or company name |
Owner name: IDEMIA FRANCE, FR Effective date: 20230206 |
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| PLFP | Fee payment |
Year of fee payment: 13 |
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| PLFP | Fee payment |
Year of fee payment: 14 |
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| PLFP | Fee payment |
Year of fee payment: 15 |