FR3097367B1 - Procede de realisation de transistors mis en œuvre a faible temperature - Google Patents

Procede de realisation de transistors mis en œuvre a faible temperature Download PDF

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Publication number
FR3097367B1
FR3097367B1 FR1906449A FR1906449A FR3097367B1 FR 3097367 B1 FR3097367 B1 FR 3097367B1 FR 1906449 A FR1906449 A FR 1906449A FR 1906449 A FR1906449 A FR 1906449A FR 3097367 B1 FR3097367 B1 FR 3097367B1
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France
Prior art keywords
layer
substrate
low temperature
jfet transistor
transistors implemented
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1906449A
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English (en)
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FR3097367A1 (fr
Inventor
Jean-Pierre Colinge
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Publication date
Application filed by Commissariat a lEnergie Atomique CEA, Commissariat a lEnergie Atomique et aux Energies Alternatives CEA filed Critical Commissariat a lEnergie Atomique CEA
Priority to FR1906449A priority Critical patent/FR3097367B1/fr
Priority to US16/902,873 priority patent/US11227800B2/en
Publication of FR3097367A1 publication Critical patent/FR3097367A1/fr
Application granted granted Critical
Publication of FR3097367B1 publication Critical patent/FR3097367B1/fr
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/051—Manufacture or treatment of FETs having PN junction gates
    • H10D30/0516—Manufacture or treatment of FETs having PN junction gates of FETs having PN heterojunction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/801—FETs having heterojunction gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1922—Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

Procédé de réalisation d’un transistor JFET (126), comprenant : a) réalisation, sur un premier substrat, d’un empilement formé d’une première couche comprenant un premier semi-conducteur dopé selon un premier type de conductivité et d’une deuxième couche comprenant un deuxième semi-conducteur dopé selon un deuxième type de conductivité, la première couche étant disposée entre le premier substrat et la deuxième couche, puis b) solidarisation de l’empilement contre un deuxième substrat (116) tel que l’empilement soit disposé entre le premier substrat et le deuxième substrat, puis c) retrait du premier substrat, puis d) gravure de la première couche telle qu’une portion restante de la première couche forme une grille avant (122) du transistor JFET, puis e) gravure de la deuxième couche telle qu’une portion restante (124) de la deuxième couche soit disposée sous la grille avant du transistor JFET et forme le canal, la source et le drain du transistor JFET. Figure pour l’abrégé : figure 1G.
FR1906449A 2019-06-17 2019-06-17 Procede de realisation de transistors mis en œuvre a faible temperature Active FR3097367B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1906449A FR3097367B1 (fr) 2019-06-17 2019-06-17 Procede de realisation de transistors mis en œuvre a faible temperature
US16/902,873 US11227800B2 (en) 2019-06-17 2020-06-16 Method for producing transistors implemented at low temperature

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1906449A FR3097367B1 (fr) 2019-06-17 2019-06-17 Procede de realisation de transistors mis en œuvre a faible temperature
FR1906449 2019-06-17

Publications (2)

Publication Number Publication Date
FR3097367A1 FR3097367A1 (fr) 2020-12-18
FR3097367B1 true FR3097367B1 (fr) 2021-07-02

Family

ID=67875712

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1906449A Active FR3097367B1 (fr) 2019-06-17 2019-06-17 Procede de realisation de transistors mis en œuvre a faible temperature

Country Status (2)

Country Link
US (1) US11227800B2 (fr)
FR (1) FR3097367B1 (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6833569B2 (en) * 2002-12-23 2004-12-21 International Business Machines Corporation Self-aligned planar double-gate process by amorphization
US10388863B2 (en) * 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
FR2961016B1 (fr) * 2010-06-07 2013-06-07 Commissariat Energie Atomique Circuit integre a dispositif de type fet sans jonction et a depletion
FR3073667B1 (fr) * 2017-11-10 2021-12-03 Commissariat Energie Atomique Circuit 3d a transistors sans jonction n et p

Also Published As

Publication number Publication date
US20200395249A1 (en) 2020-12-17
FR3097367A1 (fr) 2020-12-18
US11227800B2 (en) 2022-01-18

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