FR3139940B1 - Procédé de remplissage d’une tranchée formée dans un substrat semiconducteur - Google Patents

Procédé de remplissage d’une tranchée formée dans un substrat semiconducteur Download PDF

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Publication number
FR3139940B1
FR3139940B1 FR2209435A FR2209435A FR3139940B1 FR 3139940 B1 FR3139940 B1 FR 3139940B1 FR 2209435 A FR2209435 A FR 2209435A FR 2209435 A FR2209435 A FR 2209435A FR 3139940 B1 FR3139940 B1 FR 3139940B1
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France
Prior art keywords
layer
filling
semiconductor substrate
trench
trench formed
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Active
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FR2209435A
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English (en)
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FR3139940A1 (fr
Inventor
Bilel Saidi
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STMicroelectronics Crolles 2 SAS
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STMicroelectronics Crolles 2 SAS
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Publication date
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Priority to FR2209435A priority Critical patent/FR3139940B1/fr
Priority to US18/466,542 priority patent/US20240096620A1/en
Publication of FR3139940A1 publication Critical patent/FR3139940A1/fr
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
    • H10P14/3802—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3454—Amorphous
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3456—Polycrystalline
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/807—Pixel isolation structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering

Abstract

Procédé de remplissage d’une tranchée formée dans un substrat semiconducteur La présente description concerne un procédé de remplissage d’une tranchée formée dans un substrat semiconducteur (103), comprenant les étapes successives suivantes : a)déposer une première couche (109) de silicium dans des conditions de dépôt amorphe sur les parois latérales et au fond de la tranchée ; b) déposer une deuxième couche (111) de silicium dans des conditions de dépôt polycristallin sur et en contact avec la première couche (109) ; etc) déposer une troisième couche (113) de silicium dopé dans des conditions de dépôt amorphe sur et en contact avec la deuxième couche (111) de manière à combler entièrement la tranchée, dans lequel, à l’issue de l’étape b), la première couche (109) est en silicium polycristallin présentant une taille de grain différente de celle de la deuxième couche (111). Figure pour l'abrégé : Fig. 1F
FR2209435A 2022-09-19 2022-09-19 Procédé de remplissage d’une tranchée formée dans un substrat semiconducteur Active FR3139940B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR2209435A FR3139940B1 (fr) 2022-09-19 2022-09-19 Procédé de remplissage d’une tranchée formée dans un substrat semiconducteur
US18/466,542 US20240096620A1 (en) 2022-09-19 2023-09-13 Method of filling a trench formed in a semiconductor substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2209435A FR3139940B1 (fr) 2022-09-19 2022-09-19 Procédé de remplissage d’une tranchée formée dans un substrat semiconducteur
FR2209435 2022-09-19

Publications (2)

Publication Number Publication Date
FR3139940A1 FR3139940A1 (fr) 2024-03-22
FR3139940B1 true FR3139940B1 (fr) 2024-12-13

Family

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FR2209435A Active FR3139940B1 (fr) 2022-09-19 2022-09-19 Procédé de remplissage d’une tranchée formée dans un substrat semiconducteur

Country Status (2)

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US (1) US20240096620A1 (fr)
FR (1) FR3139940B1 (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2706469B2 (ja) * 1988-06-01 1998-01-28 松下電器産業株式会社 半導体装置の製造方法
JPH0799771B2 (ja) * 1992-06-26 1995-10-25 インターナショナル・ビジネス・マシーンズ・コーポレイション 皮膜中の応力を制御する方法
KR102821368B1 (ko) * 2019-06-21 2025-06-17 삼성전자주식회사 반도체 소자 및 그 제조 방법

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Publication number Publication date
FR3139940A1 (fr) 2024-03-22
US20240096620A1 (en) 2024-03-21

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