FR3141592B1 - Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI) - Google Patents

Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI) Download PDF

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Publication number
FR3141592B1
FR3141592B1 FR2211172A FR2211172A FR3141592B1 FR 3141592 B1 FR3141592 B1 FR 3141592B1 FR 2211172 A FR2211172 A FR 2211172A FR 2211172 A FR2211172 A FR 2211172A FR 3141592 B1 FR3141592 B1 FR 3141592B1
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FR
France
Prior art keywords
piezoelectric
substrate
poi
insulator
layer
Prior art date
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Active
Application number
FR2211172A
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English (en)
Other versions
FR3141592A1 (fr
Inventor
Isabelle Huyet
Alexis Drouin
Oleg Kononchuk
Marcel Broekaart
Luciana Capello
Brice Tavel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR2211172A priority Critical patent/FR3141592B1/fr
Priority to TW112139748A priority patent/TW202441580A/zh
Priority to CN202380075202.XA priority patent/CN120113395A/zh
Priority to KR1020257013428A priority patent/KR20250099334A/ko
Priority to PCT/EP2023/079948 priority patent/WO2024089181A1/fr
Priority to EP23794418.6A priority patent/EP4609679A1/fr
Priority to JP2025524311A priority patent/JP2026512971A/ja
Publication of FR3141592A1 publication Critical patent/FR3141592A1/fr
Application granted granted Critical
Publication of FR3141592B1 publication Critical patent/FR3141592B1/fr
Active legal-status Critical Current
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/704—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings
    • H10N30/706—Piezoelectric or electrostrictive devices based on piezoelectric or electrostrictive films or coatings characterised by the underlying bases, e.g. substrates
    • H10N30/708—Intermediate layers, e.g. barrier, adhesion or growth control buffer layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/85—Piezoelectric or electrostrictive active materials
    • H10N30/853—Ceramic compositions
    • H10N30/8542—Alkali metal based oxides, e.g. lithium, sodium or potassium niobates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

L’invention concerne un substrat piézoélectrique sur isolant (POI) (130, 138, 144, 152, 166) comprenant un substrat support (100) , comprenant une couche de piégeage (102) sur une surface libre (104) du substrat support (100)une couche piézoélectrique (114), en particulier une couche piézoélectrique (114) de Tantalate de Lithium (LTO) ou de Niobate de Lithium (LNO), une structure intermédiaire (120) positionnée en sandwich entre la couche piézoélectrique (114) et la couche de piégeage (102) du substrat support (100), dans lequel la structure intermédiaire (120) comprend au moins une couche barrière (122, 122’) de diffusion d’élément métallique à base de Nitrure de Tantale (TaN) ou de Nitrure de Carbone de Silicium (SiOxNy). L’invention concerne aussi un procédé de fabrication d’un tel substrat piézoélectrique sur isolant (POI) (130, 138, 144, 152, 166). Figure pour l’abrégé : Figure 1
FR2211172A 2022-10-26 2022-10-26 Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI) Active FR3141592B1 (fr)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR2211172A FR3141592B1 (fr) 2022-10-26 2022-10-26 Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI)
TW112139748A TW202441580A (zh) 2022-10-26 2023-10-18 絕緣體上壓電（ｐｏｉ）底材及用於製作絕緣體上壓電（ｐｏｉ）底材之方法
KR1020257013428A KR20250099334A (ko) 2022-10-26 2023-10-26 절연체 상 압전(poi) 기판, 및 절연체 상 압전(poi) 기판의 제조 방법
PCT/EP2023/079948 WO2024089181A1 (fr) 2022-10-26 2023-10-26 Substrat piézoélectrique sur isolant (poi) et procédé de fabrication d'un substrat piézoélectrique sur isolant (poi)
CN202380075202.XA CN120113395A (zh) 2022-10-26 2023-10-26 绝缘体上压电（poi）基板和制造绝缘体上压电（poi）基板的方法
EP23794418.6A EP4609679A1 (fr) 2022-10-26 2023-10-26 Substrat piézoélectrique sur isolant (poi) et procédé de fabrication d'un substrat piézoélectrique sur isolant (poi)
JP2025524311A JP2026512971A (ja) 2022-10-26 2023-10-26 圧電体オンインシュレータ（ｐｏｉ）基板、及び圧電体オンインシュレータ（ｐｏｉ）基板を製造するためのプロセス

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR2211172A FR3141592B1 (fr) 2022-10-26 2022-10-26 Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI)
FR2211172 2022-10-26

Publications (2)

Publication Number Publication Date
FR3141592A1 FR3141592A1 (fr) 2024-05-03
FR3141592B1 true FR3141592B1 (fr) 2024-10-18

Family

ID=85221968

Family Applications (1)

Application Number Title Priority Date Filing Date
FR2211172A Active FR3141592B1 (fr) 2022-10-26 2022-10-26 Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI)

Country Status (7)

Country Link
EP (1) EP4609679A1 (fr)
JP (1) JP2026512971A (fr)
KR (1) KR20250099334A (fr)
CN (1) CN120113395A (fr)
FR (1) FR3141592B1 (fr)
TW (1) TW202441580A (fr)
WO (1) WO2024089181A1 (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020036212A (ja) * 2018-08-30 2020-03-05 信越化学工業株式会社 複合基板および複合基板の製造方法
FR3094573B1 (fr) * 2019-03-29 2021-08-13 Soitec Silicon On Insulator Procede de preparation d’une couche mince de materiau ferroelectrique
FR3098642B1 (fr) * 2019-07-12 2021-06-11 Soitec Silicon On Insulator procédé de fabrication d'une structure comprenant une couche mince reportée sur un support muni d’une couche de piégeage de charges
FR3104318B1 (fr) * 2019-12-05 2023-03-03 Soitec Silicon On Insulator Procédé de formation d'un support de manipulation à haute résistivité pour substrat composite

Also Published As

Publication number Publication date
TW202441580A (zh) 2024-10-16
FR3141592A1 (fr) 2024-05-03
KR20250099334A (ko) 2025-07-01
WO2024089181A1 (fr) 2024-05-02
CN120113395A (zh) 2025-06-06
EP4609679A1 (fr) 2025-09-03
JP2026512971A (ja) 2026-04-22

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