FR3104318B1 - Procédé de formation d'un support de manipulation à haute résistivité pour substrat composite - Google Patents

Procédé de formation d'un support de manipulation à haute résistivité pour substrat composite Download PDF

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Publication number
FR3104318B1
FR3104318B1 FR1913781A FR1913781A FR3104318B1 FR 3104318 B1 FR3104318 B1 FR 3104318B1 FR 1913781 A FR1913781 A FR 1913781A FR 1913781 A FR1913781 A FR 1913781A FR 3104318 B1 FR3104318 B1 FR 3104318B1
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FR
France
Prior art keywords
forming
composite substrate
high strength
handling support
substrate
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Active
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FR1913781A
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English (en)
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FR3104318A1 (fr
Inventor
Youngpil Kim
Isabelle Bertrand
Christelle Veytizou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
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Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority to FR1913781A priority Critical patent/FR3104318B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to JP2022528307A priority patent/JP7609865B2/ja
Priority to KR1020227023105A priority patent/KR102828199B1/ko
Priority to EP20810977.7A priority patent/EP4070368B1/fr
Priority to CN202080072021.8A priority patent/CN114556526B/zh
Priority to PCT/EP2020/083379 priority patent/WO2021110513A1/fr
Priority to US17/755,812 priority patent/US12581922B2/en
Priority to TW109142789A priority patent/TWI851857B/zh
Publication of FR3104318A1 publication Critical patent/FR3104318A1/fr
Application granted granted Critical
Publication of FR3104318B1 publication Critical patent/FR3104318B1/fr
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/88—Mounts; Supports; Enclosures; Casings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3204—Materials thereof being Group IVA semiconducting materials
    • H10P14/3208—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3451—Structure
    • H10P14/3452—Microstructure
    • H10P14/3456—Polycrystalline
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

L'invention concerne un procédé de formation d'un substrat de manipulation à haute résistivité pour substrat composite, le procédé comprenant les étapes suivantes : - fournir un substrat de base en silicium ; - exposer le substrat de base à un précurseur unique de carbone à une pression inférieure à la pression atmosphérique pour former une couche de carbure de silicium polycristallin d'au moins 5 nm sur la surface du substrat de base ; et puis - faire croître une couche polycristalline de piégeage de charge sur la couche contenant du carbone. Figure à publier avec l'abrégé : Fig. 1
FR1913781A 2019-12-05 2019-12-05 Procédé de formation d'un support de manipulation à haute résistivité pour substrat composite Active FR3104318B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR1913781A FR3104318B1 (fr) 2019-12-05 2019-12-05 Procédé de formation d'un support de manipulation à haute résistivité pour substrat composite
KR1020227023105A KR102828199B1 (ko) 2019-12-05 2020-11-25 복합 기판용 고저항 핸들 지지체를 형성하는 방법
EP20810977.7A EP4070368B1 (fr) 2019-12-05 2020-11-25 Procédé de formation d'un support de manipulation à haute résistivité de substrat composite
CN202080072021.8A CN114556526B (zh) 2019-12-05 2020-11-25 形成用于复合衬底的高电阻率处理支撑体的方法
JP2022528307A JP7609865B2 (ja) 2019-12-05 2020-11-25 複合基板のための高抵抗率ハンドル支持体を形成する方法
PCT/EP2020/083379 WO2021110513A1 (fr) 2019-12-05 2020-11-25 Procédé de formation d'un support de manipulation à haute résistivité de substrat composite
US17/755,812 US12581922B2 (en) 2019-12-05 2020-11-25 Method for forming a high resistivity handle support for composite substrate
TW109142789A TWI851857B (zh) 2019-12-05 2020-12-04 形成用於複合基板之高電阻率處理支撐物的方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1913781 2019-12-05
FR1913781A FR3104318B1 (fr) 2019-12-05 2019-12-05 Procédé de formation d'un support de manipulation à haute résistivité pour substrat composite

Publications (2)

Publication Number Publication Date
FR3104318A1 FR3104318A1 (fr) 2021-06-11
FR3104318B1 true FR3104318B1 (fr) 2023-03-03

Family

ID=69811151

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1913781A Active FR3104318B1 (fr) 2019-12-05 2019-12-05 Procédé de formation d'un support de manipulation à haute résistivité pour substrat composite

Country Status (8)

Country Link
US (1) US12581922B2 (fr)
EP (1) EP4070368B1 (fr)
JP (1) JP7609865B2 (fr)
KR (1) KR102828199B1 (fr)
CN (1) CN114556526B (fr)
FR (1) FR3104318B1 (fr)
TW (1) TWI851857B (fr)
WO (1) WO2021110513A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115995389A (zh) * 2021-10-20 2023-04-21 苏州晶湛半导体有限公司 射频器件、碳化硅同质外延衬底及其制作方法
FR3141590B1 (fr) * 2022-10-26 2025-12-05 Soitec Silicon On Insulator Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI)
FR3141592B1 (fr) * 2022-10-26 2024-10-18 Soitec Silicon On Insulator Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI)
FR3141591B1 (fr) * 2022-10-26 2024-10-18 Soitec Silicon On Insulator Substrat piézoélectrique sur isolant (POI) et procédé de fabrication d’un substrat piézoélectrique sur isolant (POI)
EP4627620A1 (fr) 2022-11-29 2025-10-08 Soitec Support comprenant une couche de piegeage de charges, substrat composite comprenant un tel support et procedes de fabrication associes
JP2026511208A (ja) 2022-11-29 2026-04-10 ソイテック 電荷トラップ層を含む支持体、そのような支持体を含む複合基板、および関連する製造方法
JP2026511206A (ja) 2022-11-29 2026-04-10 ソイテック 電荷トラップ層を含む支持体、そのような支持体を含む複合基板、および関連する製造方法
FR3146020B1 (fr) 2023-02-20 2025-07-18 Soitec Silicon On Insulator Support comprenant une couche de piégeage de charges, substrat composite comprenant un tel support et procédé de fabrication associés
CN117750868B (zh) * 2024-02-20 2024-05-10 北京青禾晶元半导体科技有限责任公司 一种复合压电衬底及其制备方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2534525B2 (ja) * 1987-12-19 1996-09-18 富士通株式会社 β−炭化シリコン層の製造方法
KR920004173A (ko) * 1990-08-03 1992-03-27 정용문 전자 타자기의 용지 자동 세팅장치
US5296258A (en) 1992-09-30 1994-03-22 Northern Telecom Limited Method of forming silicon carbide
JP2010225733A (ja) * 2009-03-23 2010-10-07 Seiko Epson Corp 半導体基板の製造方法
FR2953640B1 (fr) 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
JP6749394B2 (ja) * 2015-11-20 2020-09-02 グローバルウェーハズ カンパニー リミテッドＧｌｏｂａｌＷａｆｅｒｓ Ｃｏ．，Ｌｔｄ． 滑らかな半導体表面の製造方法
EP3398346A1 (fr) 2015-12-28 2018-11-07 Koninklijke KPN N.V. Flux vidéo
JP2017139266A (ja) 2016-02-01 2017-08-10 株式会社東芝 複合基板、半導体装置、およびこれらの製造方法
FR3048306B1 (fr) 2016-02-26 2018-03-16 Soitec Support pour une structure semi-conductrice
EP4723861A2 (fr) * 2016-10-26 2026-04-08 GlobalWafers Co., Ltd. Substrat de silicium sur isolant à résistivité élevée ayant une efficacité de piégeage de charge améliorée
FR3068506B1 (fr) 2017-06-30 2020-02-21 Soitec Procede pour preparer un support pour une structure semi-conductrice
FR3091011B1 (fr) * 2018-12-21 2022-08-05 Soitec Silicon On Insulator Substrat de type semi-conducteur sur isolant pour des applications radiofréquences

Also Published As

Publication number Publication date
WO2021110513A1 (fr) 2021-06-10
CN114556526A (zh) 2022-05-27
US20220399200A1 (en) 2022-12-15
JP7609865B2 (ja) 2025-01-07
FR3104318A1 (fr) 2021-06-11
EP4070368A1 (fr) 2022-10-12
KR20220113455A (ko) 2022-08-12
EP4070368B1 (fr) 2023-11-08
TW202205521A (zh) 2022-02-01
JP2023504597A (ja) 2023-02-06
CN114556526B (zh) 2025-07-11
US12581922B2 (en) 2026-03-17
KR102828199B1 (ko) 2025-07-02
TWI851857B (zh) 2024-08-11

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