IT1022509B - Metodo di attacco di uno strato di ossido di silicio per produrre un bordo rastremato sullo stesso - Google Patents

Metodo di attacco di uno strato di ossido di silicio per produrre un bordo rastremato sullo stesso

Info

Publication number
IT1022509B
IT1022509B IT25798/74A IT2579874A IT1022509B IT 1022509 B IT1022509 B IT 1022509B IT 25798/74 A IT25798/74 A IT 25798/74A IT 2579874 A IT2579874 A IT 2579874A IT 1022509 B IT1022509 B IT 1022509B
Authority
IT
Italy
Prior art keywords
attaching
produce
layer
same
silicon oxide
Prior art date
Application number
IT25798/74A
Other languages
English (en)
Original Assignee
Rca Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rca Corp filed Critical Rca Corp
Application granted granted Critical
Publication of IT1022509B publication Critical patent/IT1022509B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers
IT25798/74A 1973-08-20 1974-07-31 Metodo di attacco di uno strato di ossido di silicio per produrre un bordo rastremato sullo stesso IT1022509B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00389718A US3839111A (en) 1973-08-20 1973-08-20 Method of etching silicon oxide to produce a tapered edge thereon

Publications (1)

Publication Number Publication Date
IT1022509B true IT1022509B (it) 1978-04-20

Family

ID=23539436

Family Applications (1)

Application Number Title Priority Date Filing Date
IT25798/74A IT1022509B (it) 1973-08-20 1974-07-31 Metodo di attacco di uno strato di ossido di silicio per produrre un bordo rastremato sullo stesso

Country Status (13)

Country Link
US (1) US3839111A (it)
JP (1) JPS5633858B2 (it)
BE (1) BE818991A (it)
BR (1) BR7406683D0 (it)
CA (1) CA1031250A (it)
DE (1) DE2439300C2 (it)
FR (1) FR2241876B1 (it)
GB (1) GB1445659A (it)
IN (1) IN139623B (it)
IT (1) IT1022509B (it)
NL (1) NL7410810A (it)
SE (1) SE389427B (it)
YU (1) YU40106B (it)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2359511C2 (de) * 1973-11-29 1987-03-05 Siemens AG, 1000 Berlin und 8000 München Verfahren zum lokalisierten Ätzen von Gräben in Siliciumkristallen
DE2432719B2 (de) * 1974-07-08 1977-06-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zum erzeugen von feinen strukturen aus aufdampfbaren materialien auf einer unterlage und anwendung des verfahrens
NL7607298A (nl) * 1976-07-02 1978-01-04 Philips Nv Werkwijze voor het vervaardigen van een inrichting en inrichting vervaardigd volgens de werkwijze.
US4052253A (en) * 1976-09-27 1977-10-04 Motorola, Inc. Semiconductor-oxide etchant
DE2658124C3 (de) * 1976-12-22 1982-05-06 Dynamit Nobel Ag, 5210 Troisdorf Verfahren zur Herstellung von Elektroschmelzkorund
NL7701559A (nl) * 1977-02-15 1978-08-17 Philips Nv Het maken van schuine hellingen aan metaal- patronen, alsmede substraat voor een geinte- greerde schakeling voorzien van een dergelijk patroon.
JPS55163860A (en) * 1979-06-06 1980-12-20 Toshiba Corp Manufacture of semiconductor device
US4351698A (en) * 1981-10-16 1982-09-28 Memorex Corporation Variable sloped etching of thin film heads
JPS5898934A (ja) * 1981-12-08 1983-06-13 Matsushita Electronics Corp 半導体装置の製造方法
JPS58216445A (ja) * 1982-06-10 1983-12-16 Nec Corp 半導体装置およびその製造方法
US4698132A (en) * 1986-09-30 1987-10-06 Rca Corporation Method of forming tapered contact openings
JP2852355B2 (ja) * 1989-06-26 1999-02-03 ステラケミファ株式会社 微細加工表面処理剤
US5928969A (en) * 1996-01-22 1999-07-27 Micron Technology, Inc. Method for controlled selective polysilicon etching
JP2000508082A (ja) * 1996-03-22 2000-06-27 メルク パテント ゲゼルシャフト ミット ベシュレンクテル ハフトング ドライエッチング後の側壁残さを除去するための溶液および方法
US6074951A (en) * 1997-05-29 2000-06-13 International Business Machines Corporation Vapor phase etching of oxide masked by resist or masking material
US5876879A (en) * 1997-05-29 1999-03-02 International Business Machines Corporation Oxide layer patterned by vapor phase etching
US5838055A (en) * 1997-05-29 1998-11-17 International Business Machines Corporation Trench sidewall patterned by vapor phase etching
US5930644A (en) * 1997-07-23 1999-07-27 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming a shallow trench isolation using oxide slope etching
US6762132B1 (en) * 2000-08-31 2004-07-13 Micron Technology, Inc. Compositions for dissolution of low-K dielectric films, and methods of use
US20050133479A1 (en) * 2003-12-19 2005-06-23 Youngner Dan W. Equipment and process for creating a custom sloped etch in a substrate
JP2007234754A (ja) * 2006-02-28 2007-09-13 Fujitsu Ltd レジストパターン形成方法及びレジストパターン形成装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1092740A (en) * 1966-07-15 1967-11-29 Standard Telephones Cables Ltd A method of masking the surface of a substrate
US3515607A (en) * 1967-06-21 1970-06-02 Western Electric Co Method of removing polymerised resist material from a substrate
US3642528A (en) * 1968-06-05 1972-02-15 Matsushita Electronics Corp Semiconductor device and method of making same
US3772102A (en) * 1969-10-27 1973-11-13 Gen Electric Method of transferring a desired pattern in silicon to a substrate layer
US3627598A (en) * 1970-02-05 1971-12-14 Fairchild Camera Instr Co Nitride passivation of mesa transistors by phosphovapox lifting
US3700508A (en) * 1970-06-25 1972-10-24 Gen Instrument Corp Fabrication of integrated microcircuit devices

Also Published As

Publication number Publication date
JPS5633858B2 (it) 1981-08-06
SE389427B (sv) 1976-11-01
DE2439300A1 (de) 1975-03-06
AU7229374A (en) 1976-02-19
DE2439300C2 (de) 1982-06-24
YU40106B (en) 1985-08-31
JPS5073574A (it) 1975-06-17
IN139623B (it) 1976-07-10
CA1031250A (en) 1978-05-16
NL7410810A (nl) 1975-02-24
BE818991A (fr) 1974-12-16
YU227474A (en) 1982-05-31
BR7406683D0 (pt) 1975-06-03
FR2241876B1 (it) 1978-01-27
GB1445659A (en) 1976-08-11
US3839111A (en) 1974-10-01
SE7409819L (it) 1975-02-21
FR2241876A1 (it) 1975-03-21

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