IT1175541B - Procedimento per la connessione a terra di dispositivi planari e circuiti integrati e prodotti cosi' ottenuti - Google Patents

Procedimento per la connessione a terra di dispositivi planari e circuiti integrati e prodotti cosi' ottenuti

Info

Publication number
IT1175541B
IT1175541B IT21553/84A IT2155384A IT1175541B IT 1175541 B IT1175541 B IT 1175541B IT 21553/84 A IT21553/84 A IT 21553/84A IT 2155384 A IT2155384 A IT 2155384A IT 1175541 B IT1175541 B IT 1175541B
Authority
IT
Italy
Prior art keywords
integrated circuits
contacts
procedure
products
earth connection
Prior art date
Application number
IT21553/84A
Other languages
English (en)
Other versions
IT8421553A1 (it
IT8421553A0 (it
Inventor
Giampiero Donzelli
Original Assignee
Telettra Lab Telefon
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telettra Lab Telefon filed Critical Telettra Lab Telefon
Priority to IT21553/84A priority Critical patent/IT1175541B/it
Publication of IT8421553A0 publication Critical patent/IT8421553A0/it
Priority to US06/742,520 priority patent/US4700467A/en
Priority to GB08515479A priority patent/GB2161650B/en
Priority to FR858509392A priority patent/FR2566581B1/fr
Priority to JP60134413A priority patent/JPS61111582A/ja
Priority to DE3522168A priority patent/DE3522168C2/de
Priority to ES544404A priority patent/ES8609818A1/es
Publication of IT8421553A1 publication Critical patent/IT8421553A1/it
Application granted granted Critical
Publication of IT1175541B publication Critical patent/IT1175541B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H10W15/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/056—Gallium arsenide
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/126—Power FETs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate

Landscapes

  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
IT21553/84A 1984-06-22 1984-06-22 Procedimento per la connessione a terra di dispositivi planari e circuiti integrati e prodotti cosi' ottenuti IT1175541B (it)

Priority Applications (7)

Application Number Priority Date Filing Date Title
IT21553/84A IT1175541B (it) 1984-06-22 1984-06-22 Procedimento per la connessione a terra di dispositivi planari e circuiti integrati e prodotti cosi' ottenuti
US06/742,520 US4700467A (en) 1984-06-22 1985-06-07 Process for grounding flat devices and integrated circuits
GB08515479A GB2161650B (en) 1984-06-22 1985-06-19 Process for providing electrical connections to and packaging of planar semiconductor devices and integrated circuits, and products so obtained
FR858509392A FR2566581B1 (fr) 1984-06-22 1985-06-20 Procede de mise a la masse de dispositifs semi-conducteurs plans et de circuits integres, et produits ainsi obtenus
JP60134413A JPS61111582A (ja) 1984-06-22 1985-06-21 平面デバイスと集積回路の接地工程及び得られた製品
DE3522168A DE3522168C2 (de) 1984-06-22 1985-06-21 Verfahren zum Masseverbinden von planaren Bauelementen und integrierten Schaltkreisen
ES544404A ES8609818A1 (es) 1984-06-22 1985-06-21 Procedimiento para la conexion a tierra de dispositivos de un solo plano y de circuitos integrados.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT21553/84A IT1175541B (it) 1984-06-22 1984-06-22 Procedimento per la connessione a terra di dispositivi planari e circuiti integrati e prodotti cosi' ottenuti

Publications (3)

Publication Number Publication Date
IT8421553A0 IT8421553A0 (it) 1984-06-22
IT8421553A1 IT8421553A1 (it) 1985-12-22
IT1175541B true IT1175541B (it) 1987-07-01

Family

ID=11183509

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21553/84A IT1175541B (it) 1984-06-22 1984-06-22 Procedimento per la connessione a terra di dispositivi planari e circuiti integrati e prodotti cosi' ottenuti

Country Status (7)

Country Link
US (1) US4700467A (it)
JP (1) JPS61111582A (it)
DE (1) DE3522168C2 (it)
ES (1) ES8609818A1 (it)
FR (1) FR2566581B1 (it)
GB (1) GB2161650B (it)
IT (1) IT1175541B (it)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2684801B1 (fr) * 1991-12-06 1997-01-24 Picogiga Sa Procede de realisation de composants semiconducteurs, notamment sur gaas ou inp, avec recuperation du substrat par voie chimique.
US5268065A (en) * 1992-12-21 1993-12-07 Motorola, Inc. Method for thinning a semiconductor wafer
JP3287279B2 (ja) 1997-09-25 2002-06-04 日本電気株式会社 半導体チップ、および該半導体チップが実装された半導体装置
US6777312B2 (en) * 2000-11-02 2004-08-17 California Institute Of Technology Wafer-level transfer of membranes in semiconductor processing
US7268081B2 (en) * 2000-11-02 2007-09-11 California Institute Of Technology Wafer-level transfer of membranes with gas-phase etching and wet etching methods
KR100407472B1 (ko) * 2001-06-29 2003-11-28 삼성전자주식회사 트렌치가 형성된 상부 칩을 구비하는 칩 적층형 패키지소자 및 그 제조 방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1933731C3 (de) * 1968-07-05 1982-03-25 Honeywell Information Systems Italia S.p.A., Caluso, Torino Verfahren zum Herstellen einer integrierten Halbleiterschaltung
US3771219A (en) * 1970-02-05 1973-11-13 Sharp Kk Method for manufacturing semiconductor device
GB1601059A (en) * 1978-05-31 1981-10-21 Secr Defence Fet devices and their fabrication
GB1602498A (en) * 1978-05-31 1981-11-11 Secr Defence Fet devices and their fabrication
JPS55545A (en) * 1979-02-13 1980-01-05 Canon Inc Production of electrophotographic photoreceptor
IT8048031A0 (it) * 1979-04-09 1980-02-28 Raytheon Co Perfezionamento nei dispositivi a semiconduttore ad effetto di campo
JPS5749252A (en) * 1980-09-09 1982-03-23 Matsushita Electronics Corp Manufacture of semiconductor device
JPS5817626A (ja) * 1981-07-13 1983-02-01 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン 低温度ダイ取り付け方法

Also Published As

Publication number Publication date
GB8515479D0 (en) 1985-07-24
ES8609818A1 (es) 1986-09-01
ES544404A0 (es) 1986-09-01
FR2566581B1 (fr) 1989-12-29
IT8421553A1 (it) 1985-12-22
FR2566581A1 (fr) 1985-12-27
IT8421553A0 (it) 1984-06-22
JPS61111582A (ja) 1986-05-29
GB2161650B (en) 1988-07-13
GB2161650A (en) 1986-01-15
DE3522168A1 (de) 1986-01-16
DE3522168C2 (de) 1994-05-11
US4700467A (en) 1987-10-20

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