IT1206469B - Procedimento per fabbricare un dispositivo a circuito integrato a semiconduttori. - Google Patents

Procedimento per fabbricare un dispositivo a circuito integrato a semiconduttori.

Info

Publication number
IT1206469B
IT1206469B IT8423631A IT2363184A IT1206469B IT 1206469 B IT1206469 B IT 1206469B IT 8423631 A IT8423631 A IT 8423631A IT 2363184 A IT2363184 A IT 2363184A IT 1206469 B IT1206469 B IT 1206469B
Authority
IT
Italy
Prior art keywords
procedure
manufacturing
integrated circuit
semiconductor integrated
circuit device
Prior art date
Application number
IT8423631A
Other languages
English (en)
Other versions
IT8423631A0 (it
Inventor
Akihiro Tomozawa
Yoku Kaino
Shigeru Shimada
Nozomi Horino
Yoshiaki Yoshiura
Osamu Tsuchiya
Shozo Hosoda
Original Assignee
Hitachi Ltd
Hitachi Microcumputer Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcumputer Eng filed Critical Hitachi Ltd
Publication of IT8423631A0 publication Critical patent/IT8423631A0/it
Application granted granted Critical
Publication of IT1206469B publication Critical patent/IT1206469B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
IT8423631A 1983-11-18 1984-11-16 Procedimento per fabbricare un dispositivo a circuito integrato a semiconduttori. IT1206469B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58216319A JPS60109250A (ja) 1983-11-18 1983-11-18 半導体集積回路装置

Publications (2)

Publication Number Publication Date
IT8423631A0 IT8423631A0 (it) 1984-11-16
IT1206469B true IT1206469B (it) 1989-04-27

Family

ID=16686661

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8423631A IT1206469B (it) 1983-11-18 1984-11-16 Procedimento per fabbricare un dispositivo a circuito integrato a semiconduttori.

Country Status (2)

Country Link
JP (1) JPS60109250A (it)
IT (1) IT1206469B (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0828419B2 (ja) * 1986-02-20 1996-03-21 富士通株式会社 配線構造

Also Published As

Publication number Publication date
IT8423631A0 (it) 1984-11-16
JPS60109250A (ja) 1985-06-14

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19951128