IT1225612B - Processo di fabbricazione di dispositivi integrati cmos con lunghezza di gate ridotta e transistori a canale superficiale - Google Patents

Processo di fabbricazione di dispositivi integrati cmos con lunghezza di gate ridotta e transistori a canale superficiale

Info

Publication number
IT1225612B
IT1225612B IT8883653A IT8365388A IT1225612B IT 1225612 B IT1225612 B IT 1225612B IT 8883653 A IT8883653 A IT 8883653A IT 8365388 A IT8365388 A IT 8365388A IT 1225612 B IT1225612 B IT 1225612B
Authority
IT
Italy
Prior art keywords
manufacturing process
gate length
channel transistors
cmos devices
surface channel
Prior art date
Application number
IT8883653A
Other languages
English (en)
Other versions
IT8883653A0 (it
Inventor
Carlo Bergonzoni
Giuseppe Paolo Crisenza
Tiziana Cavioni
Original Assignee
Sgs Thomson Microelectronics
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Thomson Microelectronics filed Critical Sgs Thomson Microelectronics
Priority to IT8883653A priority Critical patent/IT1225612B/it
Publication of IT8883653A0 publication Critical patent/IT8883653A0/it
Priority to EP19890830330 priority patent/EP0362147A3/en
Priority to US07/381,283 priority patent/US4987088A/en
Priority to JP1196482A priority patent/JPH0276255A/ja
Application granted granted Critical
Publication of IT1225612B publication Critical patent/IT1225612B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
IT8883653A 1988-07-29 1988-07-29 Processo di fabbricazione di dispositivi integrati cmos con lunghezza di gate ridotta e transistori a canale superficiale IT1225612B (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT8883653A IT1225612B (it) 1988-07-29 1988-07-29 Processo di fabbricazione di dispositivi integrati cmos con lunghezza di gate ridotta e transistori a canale superficiale
EP19890830330 EP0362147A3 (en) 1988-07-29 1989-07-17 Fabrication of cmos integrated devices with reduced gate length
US07/381,283 US4987088A (en) 1988-07-29 1989-07-18 Fabrication of CMOS devices with reduced gate length
JP1196482A JPH0276255A (ja) 1988-07-29 1989-07-28 短いゲート長さを有するｃｍｏｓデバイスの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8883653A IT1225612B (it) 1988-07-29 1988-07-29 Processo di fabbricazione di dispositivi integrati cmos con lunghezza di gate ridotta e transistori a canale superficiale

Publications (2)

Publication Number Publication Date
IT8883653A0 IT8883653A0 (it) 1988-07-29
IT1225612B true IT1225612B (it) 1990-11-22

Family

ID=11323664

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8883653A IT1225612B (it) 1988-07-29 1988-07-29 Processo di fabbricazione di dispositivi integrati cmos con lunghezza di gate ridotta e transistori a canale superficiale

Country Status (4)

Country Link
US (1) US4987088A (it)
EP (1) EP0362147A3 (it)
JP (1) JPH0276255A (it)
IT (1) IT1225612B (it)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04252032A (ja) * 1990-05-24 1992-09-08 Micron Technol Inc Ｎウエルスチーム酸化工程を省略し、ブランケットｐウエル打ち込み工程によりシリコン基板上にｎウエルおよびｐウエルを形成させる方法
JP3879173B2 (ja) * 1996-03-25 2007-02-07 住友電気工業株式会社 化合物半導体気相成長方法
US5883544A (en) * 1996-12-03 1999-03-16 Stmicroelectronics, Inc. Integrated circuit actively biasing the threshold voltage of transistors and related methods
US5939934A (en) * 1996-12-03 1999-08-17 Stmicroelectronics, Inc. Integrated circuit passively biasing transistor effective threshold voltage and related methods
US5834966A (en) * 1996-12-08 1998-11-10 Stmicroelectronics, Inc. Integrated circuit sensing and digitally biasing the threshold voltage of transistors and related methods
US5929695A (en) * 1997-06-02 1999-07-27 Stmicroelectronics, Inc. Integrated circuit having selective bias of transistors for low voltage and low standby current and related methods
FR2794898B1 (fr) 1999-06-11 2001-09-14 France Telecom Dispositif semi-conducteur a tension de seuil compensee et procede de fabrication
US10903210B2 (en) * 2015-05-05 2021-01-26 International Business Machines Corporation Sub-fin doped bulk fin field effect transistor (FinFET), Integrated Circuit (IC) and method of manufacture

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4075754A (en) * 1974-02-26 1978-02-28 Harris Corporation Self aligned gate for di-CMOS
DE3133841A1 (de) * 1981-08-27 1983-03-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
US4613885A (en) * 1982-02-01 1986-09-23 Texas Instruments Incorporated High-voltage CMOS process
US4598460A (en) * 1984-12-10 1986-07-08 Solid State Scientific, Inc. Method of making a CMOS EPROM with independently selectable thresholds
US4745083A (en) * 1986-11-19 1988-05-17 Sprague Electric Company Method of making a fast IGFET
US4839301A (en) * 1988-12-19 1989-06-13 Micron Technology, Inc. Blanket CMOS channel stop implant employing a combination of n-channel and p-channel punch-through implants

Also Published As

Publication number Publication date
EP0362147A3 (en) 1991-01-23
IT8883653A0 (it) 1988-07-29
US4987088A (en) 1991-01-22
EP0362147A2 (en) 1990-04-04
JPH0276255A (ja) 1990-03-15

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970730