IT1257387B - Procedimento di misura per circuiti integrati. - Google Patents

Procedimento di misura per circuiti integrati.

Info

Publication number
IT1257387B
IT1257387B ITTO920622A ITTO920622A IT1257387B IT 1257387 B IT1257387 B IT 1257387B IT TO920622 A ITTO920622 A IT TO920622A IT TO920622 A ITTO920622 A IT TO920622A IT 1257387 B IT1257387 B IT 1257387B
Authority
IT
Italy
Prior art keywords
integrated circuits
circuit
circuit blocks
measurement
measurement procedure
Prior art date
Application number
ITTO920622A
Other languages
English (en)
Inventor
Kazuhiro Nishimura
Kiyotoshi Ueda
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITTO920622A0 publication Critical patent/ITTO920622A0/it
Publication of ITTO920622A1 publication Critical patent/ITTO920622A1/it
Application granted granted Critical
Publication of IT1257387B publication Critical patent/IT1257387B/it

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

Un procedimento per la misura dei circuiti integrati comprende le operazioni di: posizionare una pluralità di circuiti integrati ciascuno dei quali può essere suddiviso in una pluralità di blocchi di circuito a seconda della funzione; selezionare blocchi di circuito diversi in circuiti integrati diversi; misurare i risultati di prova a partire da ciascuno dei blocchi di circuito selezionati tramite un'unità di misura; e selezionare un blocco di circuito diverso dal blocco di circuito precedentemente selezionato in ciascuno dei circuiti integrati per la successiva misura, realizzata sostanzialmente nella stessa maniera della misura precedente. La selezione dei blocchi di circuito in ciascuno dei circuiti integrati viene controllata da un circuito a matrice. In alternativa, essa viene determinata dalla posizione del circuito integrato a cui il blocco appartiene. (Figura 1)
ITTO920622A 1991-07-23 1992-07-21 Procedimento di misura per circuiti integrati. IT1257387B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3182444A JP2641816B2 (ja) 1991-07-23 1991-07-23 半導体集積回路の測定方法

Publications (3)

Publication Number Publication Date
ITTO920622A0 ITTO920622A0 (it) 1992-07-21
ITTO920622A1 ITTO920622A1 (it) 1994-01-21
IT1257387B true IT1257387B (it) 1996-01-15

Family

ID=16118377

Family Applications (1)

Application Number Title Priority Date Filing Date
ITTO920622A IT1257387B (it) 1991-07-23 1992-07-21 Procedimento di misura per circuiti integrati.

Country Status (3)

Country Link
US (1) US5386189A (it)
JP (1) JP2641816B2 (it)
IT (1) IT1257387B (it)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5563524A (en) * 1989-05-19 1996-10-08 A.T.E. Solutions, Inc. Apparatus for testing electric circuits
EP0653072B1 (en) * 1992-07-27 2004-07-14 Credence Systems Corporation Apparatus for automatic testing of complex devices
EP1326085A3 (en) * 1993-11-08 2007-11-14 Honda Giken Kogyo Kabushiki Kaisha Apparatus for inspecting electric component for inverter circuit
US5608337A (en) * 1995-06-07 1997-03-04 Altera Corporation Method and apparatus of testing an integrated circuit device
US6476628B1 (en) * 1999-06-28 2002-11-05 Teradyne, Inc. Semiconductor parallel tester
US7342405B2 (en) * 2000-01-18 2008-03-11 Formfactor, Inc. Apparatus for reducing power supply noise in an integrated circuit
US6657455B2 (en) * 2000-01-18 2003-12-02 Formfactor, Inc. Predictive, adaptive power supply for an integrated circuit under test
DE10002831C2 (de) * 2000-01-24 2002-01-03 Infineon Technologies Ag Verfahren und Vorrichtung zum Testen elektronischer Bauelemente
US6476631B1 (en) * 2001-06-29 2002-11-05 Lsi Logic Corporation Defect screening using delta VDD
CN100337119C (zh) * 2003-03-10 2007-09-12 盛群半导体股份有限公司 集成电路的检测方法
US7151389B2 (en) * 2004-03-05 2006-12-19 Qualitau, Inc. Dual channel source measurement unit for semiconductor device testing
WO2006064551A1 (ja) * 2004-12-14 2006-06-22 Atsunori Shibuya 試験装置
DE102005011512A1 (de) * 2005-03-10 2006-09-21 Endress + Hauser Wetzer Gmbh + Co. Kg Signalausgabeeinheit
US7208969B2 (en) * 2005-07-06 2007-04-24 Optimaltest Ltd. Optimize parallel testing
US7528622B2 (en) * 2005-07-06 2009-05-05 Optimal Test Ltd. Methods for slow test time detection of an integrated circuit during parallel testing
KR100835466B1 (ko) * 2006-12-08 2008-06-04 동부일렉트로닉스 주식회사 반도체 테스트장치의 핀 일렉트로닉스 확장 구조
KR100916762B1 (ko) * 2007-12-10 2009-09-14 주식회사 아이티엔티 반도체 디바이스 테스트 시스템
US8112249B2 (en) 2008-12-22 2012-02-07 Optimaltest Ltd. System and methods for parametric test time reduction
KR102388044B1 (ko) * 2015-10-19 2022-04-19 삼성전자주식회사 테스트 장치 및 이를 포함하는 테스트 시스템

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4300207A (en) * 1979-09-25 1981-11-10 Grumman Aerospace Corporation Multiple matrix switching system
JPS5661136A (en) * 1979-10-25 1981-05-26 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor test equipment
US4404519A (en) * 1980-12-10 1983-09-13 International Business Machine Company Testing embedded arrays in large scale integrated circuits
US4402055A (en) * 1981-01-27 1983-08-30 Westinghouse Electric Corp. Automatic test system utilizing interchangeable test devices
US4481627A (en) * 1981-10-30 1984-11-06 Honeywell Information Systems Inc. Embedded memory testing method and apparatus
US4724379A (en) * 1984-03-14 1988-02-09 Teradyne, Inc. Relay multiplexing for circuit testers
US4639664A (en) * 1984-05-31 1987-01-27 Texas Instruments Incorporated Apparatus for testing a plurality of integrated circuits in parallel
GB8432533D0 (en) * 1984-12-21 1985-02-06 Plessey Co Plc Integrated circuits
US4719411A (en) * 1985-05-13 1988-01-12 California Institute Of Technology Addressable test matrix for measuring analog transfer characteristics of test elements used for integrated process control and device evaluation
US5126953A (en) * 1986-06-27 1992-06-30 Berger James K Printed circuit board assembly tester
US5025210A (en) * 1986-07-18 1991-06-18 Kabushiki Kaisha Toshiba Evaluation facilitating circuit device
US5034685A (en) * 1988-05-16 1991-07-23 Leedy Glenn J Test device for testing integrated circuits
US4926363A (en) * 1988-09-30 1990-05-15 Advanced Micro Devices, Inc. Modular test structure for single chip digital exchange controller
US5025205A (en) * 1989-06-22 1991-06-18 Texas Instruments Incorporated Reconfigurable architecture for logic test system

Also Published As

Publication number Publication date
JP2641816B2 (ja) 1997-08-20
US5386189A (en) 1995-01-31
ITTO920622A0 (it) 1992-07-21
ITTO920622A1 (it) 1994-01-21
JPH0526985A (ja) 1993-02-05

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Legal Events

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0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970730