IT1270035B - Sistema di controllori di interruzioni programmabile a piu' processoricon un controllore di interruzioni locale integrato nei processori - Google Patents

Sistema di controllori di interruzioni programmabile a piu' processoricon un controllore di interruzioni locale integrato nei processori

Info

Publication number
IT1270035B
IT1270035B ITMI940730A ITMI940730A IT1270035B IT 1270035 B IT1270035 B IT 1270035B IT MI940730 A ITMI940730 A IT MI940730A IT MI940730 A ITMI940730 A IT MI940730A IT 1270035 B IT1270035 B IT 1270035B
Authority
IT
Italy
Prior art keywords
interruption controller
processors
multiple processor
programmable
local
Prior art date
Application number
ITMI940730A
Other languages
English (en)
Inventor
P K Nizar
David Carson
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of ITMI940730A0 publication Critical patent/ITMI940730A0/it
Publication of ITMI940730A1 publication Critical patent/ITMI940730A1/it
Application granted granted Critical
Publication of IT1270035B publication Critical patent/IT1270035B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4818—Priority circuits therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Programmable Controllers (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)
ITMI940730A 1993-04-19 1994-04-15 Sistema di controllori di interruzioni programmabile a piu' processoricon un controllore di interruzioni locale integrato nei processori IT1270035B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US4951593A 1993-04-19 1993-04-19

Publications (3)

Publication Number Publication Date
ITMI940730A0 ITMI940730A0 (it) 1994-04-15
ITMI940730A1 ITMI940730A1 (it) 1995-10-15
IT1270035B true IT1270035B (it) 1997-04-28

Family

ID=21960233

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI940730A IT1270035B (it) 1993-04-19 1994-04-15 Sistema di controllori di interruzioni programmabile a piu' processoricon un controllore di interruzioni locale integrato nei processori

Country Status (6)

Country Link
JP (1) JPH06324996A (it)
DE (1) DE4413459C2 (it)
GB (1) GB2277388B (it)
HK (1) HK1001011A1 (it)
IT (1) IT1270035B (it)
SG (1) SG48803A1 (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2298503B (en) * 1993-12-16 1998-08-12 Intel Corp Multiple programmable interrupt controllers in a computer system
US7689747B2 (en) * 2005-03-28 2010-03-30 Microsoft Corporation Systems and methods for an augmented interrupt controller and synthetic interrupt sources
JP5243711B2 (ja) 2006-11-10 2013-07-24 セイコーエプソン株式会社 プロセッサ
US7627706B2 (en) * 2007-09-06 2009-12-01 Intel Corporation Creation of logical APIC ID with cluster ID and intra-cluster ID
JP5322567B2 (ja) * 2008-10-02 2013-10-23 ルネサスエレクトロニクス株式会社 データ処理システム及び半導体集積回路
JP5169731B2 (ja) * 2008-10-24 2013-03-27 富士通セミコンダクター株式会社 マルチプロセッサシステムｌｓｉ
US8103816B2 (en) * 2008-10-28 2012-01-24 Intel Corporation Technique for communicating interrupts in a computer system
US8234431B2 (en) * 2009-10-13 2012-07-31 Empire Technology Development Llc Interrupt masking for multi-core processors
CN117294538B (zh) * 2023-11-27 2024-04-02 华信咨询设计研究院有限公司 一种数据安全风险行为的旁路检测与阻断方法及系统

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3676861A (en) * 1970-12-30 1972-07-11 Honeywell Inf Systems Multiple mask registers for servicing interrupts in a multiprocessor system
US4495569A (en) * 1982-06-28 1985-01-22 Mitsubishi Denki Kabushiki Kaisha Interrupt control for multiprocessor system with storage data controlling processor interrupted by devices
JPH03122742A (ja) * 1989-10-05 1991-05-24 Oki Electric Ind Co Ltd 割込み通知方式
US5193187A (en) * 1989-12-29 1993-03-09 Supercomputer Systems Limited Partnership Fast interrupt mechanism for interrupting processors in parallel in a multiprocessor system wherein processors are assigned process ID numbers
US5179707A (en) * 1990-06-01 1993-01-12 At&T Bell Laboratories Interrupt processing allocation in a multiprocessor system
US5125093A (en) * 1990-08-14 1992-06-23 Nexgen Microsystems Interrupt control for multiprocessor computer system

Also Published As

Publication number Publication date
DE4413459C2 (de) 2000-04-06
GB2277388A (en) 1994-10-26
ITMI940730A1 (it) 1995-10-15
SG48803A1 (en) 1998-05-18
HK1001011A1 (en) 1998-05-15
ITMI940730A0 (it) 1994-04-15
JPH06324996A (ja) 1994-11-25
DE4413459A1 (de) 1994-10-20
GB9402811D0 (en) 1994-04-06
GB2277388B (en) 1997-08-13

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970327