JPH06324996A - 集積回路およびプログラマブル・マルチ・プロセッサ割り込みコントローラ・システム - Google Patents
集積回路およびプログラマブル・マルチ・プロセッサ割り込みコントローラ・システムInfo
- Publication number
- JPH06324996A JPH06324996A JP6104748A JP10474894A JPH06324996A JP H06324996 A JPH06324996 A JP H06324996A JP 6104748 A JP6104748 A JP 6104748A JP 10474894 A JP10474894 A JP 10474894A JP H06324996 A JPH06324996 A JP H06324996A
- Authority
- JP
- Japan
- Prior art keywords
- interrupt
- processor
- bus
- controller
- mpic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
- G06F9/4818—Priority circuits therefor
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- Bus Control (AREA)
- Programmable Controllers (AREA)
- Information Transfer Systems (AREA)
- Multi Processors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US4951593A | 1993-04-19 | 1993-04-19 | |
| US049515 | 1993-04-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06324996A true JPH06324996A (ja) | 1994-11-25 |
Family
ID=21960233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6104748A Pending JPH06324996A (ja) | 1993-04-19 | 1994-04-19 | 集積回路およびプログラマブル・マルチ・プロセッサ割り込みコントローラ・システム |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH06324996A (it) |
| DE (1) | DE4413459C2 (it) |
| GB (1) | GB2277388B (it) |
| HK (1) | HK1001011A1 (it) |
| IT (1) | IT1270035B (it) |
| SG (1) | SG48803A1 (it) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008535099A (ja) * | 2005-03-28 | 2008-08-28 | マイクロソフト コーポレーション | 拡張割込み制御装置および合成割込みソースに関するシステムおよび方法 |
| JP2010086456A (ja) * | 2008-10-02 | 2010-04-15 | Renesas Technology Corp | データ処理システム及び半導体集積回路 |
| JP2010102540A (ja) * | 2008-10-24 | 2010-05-06 | Fujitsu Microelectronics Ltd | マルチプロセッサシステムlsi |
| JP2010538373A (ja) * | 2007-09-06 | 2010-12-09 | インテル・コーポレーション | クラスタidとイントラクラスタidとを有する論理apicidの作成 |
| US7853743B2 (en) | 2006-11-10 | 2010-12-14 | Seiko Epson Corporation | Processor and interrupt controlling method |
| JP2012507080A (ja) * | 2008-10-28 | 2012-03-22 | インテル・コーポレーション | コンピュータシステムにおける割り込み通信技術 |
| JP2013507719A (ja) * | 2009-10-13 | 2013-03-04 | エンパイア テクノロジー ディベロップメント エルエルシー | マルチコアプロセッサのための割込みマスク |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2298503B (en) * | 1993-12-16 | 1998-08-12 | Intel Corp | Multiple programmable interrupt controllers in a computer system |
| CN117294538B (zh) * | 2023-11-27 | 2024-04-02 | 华信咨询设计研究院有限公司 | 一种数据安全风险行为的旁路检测与阻断方法及系统 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3676861A (en) * | 1970-12-30 | 1972-07-11 | Honeywell Inf Systems | Multiple mask registers for servicing interrupts in a multiprocessor system |
| US4495569A (en) * | 1982-06-28 | 1985-01-22 | Mitsubishi Denki Kabushiki Kaisha | Interrupt control for multiprocessor system with storage data controlling processor interrupted by devices |
| JPH03122742A (ja) * | 1989-10-05 | 1991-05-24 | Oki Electric Ind Co Ltd | 割込み通知方式 |
| US5193187A (en) * | 1989-12-29 | 1993-03-09 | Supercomputer Systems Limited Partnership | Fast interrupt mechanism for interrupting processors in parallel in a multiprocessor system wherein processors are assigned process ID numbers |
| US5179707A (en) * | 1990-06-01 | 1993-01-12 | At&T Bell Laboratories | Interrupt processing allocation in a multiprocessor system |
| US5125093A (en) * | 1990-08-14 | 1992-06-23 | Nexgen Microsystems | Interrupt control for multiprocessor computer system |
-
1994
- 1994-02-14 GB GB9402811A patent/GB2277388B/en not_active Expired - Lifetime
- 1994-02-14 SG SG1996001861A patent/SG48803A1/en unknown
- 1994-04-15 IT ITMI940730A patent/IT1270035B/it active IP Right Grant
- 1994-04-18 DE DE4413459A patent/DE4413459C2/de not_active Expired - Fee Related
- 1994-04-19 JP JP6104748A patent/JPH06324996A/ja active Pending
-
1997
- 1997-12-23 HK HK97102605A patent/HK1001011A1/xx not_active IP Right Cessation
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008535099A (ja) * | 2005-03-28 | 2008-08-28 | マイクロソフト コーポレーション | 拡張割込み制御装置および合成割込みソースに関するシステムおよび方法 |
| US7853743B2 (en) | 2006-11-10 | 2010-12-14 | Seiko Epson Corporation | Processor and interrupt controlling method |
| JP2010538373A (ja) * | 2007-09-06 | 2010-12-09 | インテル・コーポレーション | クラスタidとイントラクラスタidとを有する論理apicidの作成 |
| JP2010086456A (ja) * | 2008-10-02 | 2010-04-15 | Renesas Technology Corp | データ処理システム及び半導体集積回路 |
| JP2010102540A (ja) * | 2008-10-24 | 2010-05-06 | Fujitsu Microelectronics Ltd | マルチプロセッサシステムlsi |
| US8549200B2 (en) | 2008-10-24 | 2013-10-01 | Fujitsu Semiconductor Limited | Multiprocessor system configured as system LSI |
| JP2012507080A (ja) * | 2008-10-28 | 2012-03-22 | インテル・コーポレーション | コンピュータシステムにおける割り込み通信技術 |
| JP2014029702A (ja) * | 2008-10-28 | 2014-02-13 | Intel Corp | 割り込み通信装置、方法、およびシステム |
| CN104021109A (zh) * | 2008-10-28 | 2014-09-03 | 英特尔公司 | 用于在计算机系统中传递中断的技术 |
| CN104021109B (zh) * | 2008-10-28 | 2017-11-07 | 英特尔公司 | 用于在计算机系统中传递中断的技术 |
| JP2013507719A (ja) * | 2009-10-13 | 2013-03-04 | エンパイア テクノロジー ディベロップメント エルエルシー | マルチコアプロセッサのための割込みマスク |
Also Published As
| Publication number | Publication date |
|---|---|
| IT1270035B (it) | 1997-04-28 |
| DE4413459C2 (de) | 2000-04-06 |
| GB2277388A (en) | 1994-10-26 |
| ITMI940730A1 (it) | 1995-10-15 |
| SG48803A1 (en) | 1998-05-18 |
| HK1001011A1 (en) | 1998-05-15 |
| ITMI940730A0 (it) | 1994-04-15 |
| DE4413459A1 (de) | 1994-10-20 |
| GB9402811D0 (en) | 1994-04-06 |
| GB2277388B (en) | 1997-08-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2855298B2 (ja) | 割込み要求の仲裁方法およびマルチプロセッサシステム | |
| US5696976A (en) | Protocol for interrupt bus arbitration in a multi-processor system | |
| KR100292660B1 (ko) | 프로세서가통합된인터럽트제어기를갖춘멀티프로세서프로그래머블인터럽트제어기시스템 | |
| US5555420A (en) | Multiprocessor programmable interrupt controller system with separate interrupt bus and bus retry management | |
| KR100399385B1 (ko) | 적응성인터럽트맵핑메카니즘및방법을사용하는다중처리시스템 | |
| US5555430A (en) | Interrupt control architecture for symmetrical multiprocessing system | |
| US5781187A (en) | Interrupt transmission via specialized bus cycle within a symmetrical multiprocessing system | |
| US5530891A (en) | System management interrupt mechanism within a symmetrical multiprocessing system | |
| US5564060A (en) | Interrupt handling mechanism to prevent spurious interrupts in a symmetrical multiprocessing system | |
| US4782439A (en) | Direct memory access system for microcontroller | |
| US5410710A (en) | Multiprocessor programmable interrupt controller system adapted to functional redundancy checking processor systems | |
| CA2349662C (en) | Interrupt architecture for a non-uniform memory access (numa) data processing system | |
| EP0426413B1 (en) | Multiprocessor arbitration in single processor arbitration schemes | |
| US5568649A (en) | Interrupt cascading and priority configuration for a symmetrical multiprocessing system | |
| US5701495A (en) | Scalable system interrupt structure for a multi-processing system | |
| US5613126A (en) | Timer tick auto-chaining technique within a symmetrical multiprocessing system | |
| US4953072A (en) | Node for servicing interrupt request messages on a pended bus | |
| US6249830B1 (en) | Method and apparatus for distributing interrupts in a scalable symmetric multiprocessor system without changing the bus width or bus protocol | |
| EP0685798B1 (en) | Interrupt controllers in symmetrical multiprocessing systems | |
| US5428794A (en) | Interrupting node for providing interrupt requests to a pended bus | |
| WO1994008313A1 (en) | Arrangement of dma, interrupt and timer functions to implement symmetrical processing in a multiprocessor computer system | |
| US5146597A (en) | Apparatus and method for servicing interrupts utilizing a pended bus | |
| CN118885307A (zh) | 共享资源的访问控制方法及装置、存储介质及电子设备 | |
| JPH06324996A (ja) | 集積回路およびプログラマブル・マルチ・プロセッサ割り込みコントローラ・システム | |
| US5590338A (en) | Combined multiprocessor interrupt controller and interprocessor communication mechanism |