IT1271902B - Dispositivo di memoria a semiconduttore per l'interconnessione di un circuito interno e un conduttore di alimentazione - Google Patents

Dispositivo di memoria a semiconduttore per l'interconnessione di un circuito interno e un conduttore di alimentazione

Info

Publication number
IT1271902B
IT1271902B ITMI930003A ITMI930003A IT1271902B IT 1271902 B IT1271902 B IT 1271902B IT MI930003 A ITMI930003 A IT MI930003A IT MI930003 A ITMI930003 A IT MI930003A IT 1271902 B IT1271902 B IT 1271902B
Authority
IT
Italy
Prior art keywords
interconnection
memory device
rods
semiconductor memory
internal circuit
Prior art date
Application number
ITMI930003A
Other languages
English (en)
Inventor
Kenji Kubo
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI930003A0 publication Critical patent/ITMI930003A0/it
Publication of ITMI930003A1 publication Critical patent/ITMI930003A1/it
Application granted granted Critical
Publication of IT1271902B publication Critical patent/IT1271902B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/482—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes for individual devices provided for in groups H10D8/00 - H10D48/00, e.g. for power transistors
    • H10W20/484—Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/641—Adaptable interconnections, e.g. fuses or antifuses

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Catching Or Destruction (AREA)

Abstract

Il dispositivo per impedire l'atterraggio di uccelli su una superficie comprende un elemento lastriforme dal quale si sviluppano una pluralità di aste ad esso solidalmente connesse su due file parallele, le quali sono tra loro sfalsate di una quantità atta a rendere le aste tutte equidistanti una dall'altra; l'elemento lastriforme presenta inoltre, dalla parte rivolta verso le aste, almeno prime e seconde incisioni rettilinee definenti contemporaneamente canali di scolo dell'acqua e linee di rottura facilitata per la sua suddivisione in moduli presentanti ciascuno una singola asta con la sua relativa base di appoggio.
ITMI930003A 1992-01-06 1993-01-05 Dispositivo di memoria a semiconduttore per l'interconnessione di un circuito interno e un conduttore di alimentazione IT1271902B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4000307A JP2681427B2 (ja) 1992-01-06 1992-01-06 半導体装置

Publications (3)

Publication Number Publication Date
ITMI930003A0 ITMI930003A0 (it) 1993-01-05
ITMI930003A1 ITMI930003A1 (it) 1994-07-05
IT1271902B true IT1271902B (it) 1997-06-10

Family

ID=11470251

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI930003A IT1271902B (it) 1992-01-06 1993-01-05 Dispositivo di memoria a semiconduttore per l'interconnessione di un circuito interno e un conduttore di alimentazione

Country Status (5)

Country Link
US (1) US5334866A (it)
JP (1) JP2681427B2 (it)
KR (1) KR930017122A (it)
DE (1) DE4244083C2 (it)
IT (1) IT1271902B (it)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5812031A (en) * 1996-11-06 1998-09-22 Fujitsu Limited Ring oscillator having logic gates interconnected by spiral signal lines
JPH10200050A (ja) * 1997-01-06 1998-07-31 Mitsubishi Electric Corp 半導体集積装置
US6246107B1 (en) 1999-07-07 2001-06-12 Philips Semiconductors, Inc. Semiconductor device arrangement having configuration via adjacent bond pad coding
US7023090B2 (en) * 2003-01-29 2006-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding pad and via structure design
JP2005128002A (ja) * 2003-10-01 2005-05-19 Olympus Corp エンコーダ
US9147659B1 (en) * 2005-12-27 2015-09-29 Advanced Micro Devices, Inc. Bondpad arrangement with reinforcing structures between the bondpads
WO2014190005A1 (en) * 2013-05-22 2014-11-27 Transient Electronics, Inc. Controlled transformation of non-transient electronics

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043855A (ja) * 1983-08-19 1985-03-08 Nec Corp 半導体集積回路
US4558345A (en) * 1983-10-27 1985-12-10 Rca Corporation Multiple connection bond pad for an integrated circuit device and method of making same
JPS62104065A (ja) * 1985-10-30 1987-05-14 Nippon Seiki Co Ltd 混成集積回路
JPS6412569A (en) * 1987-07-07 1989-01-17 Nec Corp Integrated circuit device
JP2647188B2 (ja) * 1989-03-20 1997-08-27 株式会社東芝 半導体装置の製造方法
JPH04188643A (ja) * 1990-11-19 1992-07-07 Nec Corp 半導体集積回路

Also Published As

Publication number Publication date
DE4244083C2 (de) 1996-05-15
KR930017122A (ko) 1993-08-30
ITMI930003A1 (it) 1994-07-05
ITMI930003A0 (it) 1993-01-05
DE4244083A1 (en) 1993-07-08
JPH05183055A (ja) 1993-07-23
US5334866A (en) 1994-08-02
JP2681427B2 (ja) 1997-11-26

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960130