IT1272817B - Procedimento per il montaggio di circuiti integrati su pannelli di circuiti stampati - Google Patents

Procedimento per il montaggio di circuiti integrati su pannelli di circuiti stampati

Info

Publication number
IT1272817B
IT1272817B ITRM940544A ITRM940544A IT1272817B IT 1272817 B IT1272817 B IT 1272817B IT RM940544 A ITRM940544 A IT RM940544A IT RM940544 A ITRM940544 A IT RM940544A IT 1272817 B IT1272817 B IT 1272817B
Authority
IT
Italy
Prior art keywords
printed circuit
chip
apply
circuit board
protective resin
Prior art date
Application number
ITRM940544A
Other languages
English (en)
Inventor
Maurizio Pugnotti
Original Assignee
Consorzio Eagle
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Consorzio Eagle filed Critical Consorzio Eagle
Priority to ITRM940544A priority Critical patent/IT1272817B/it
Publication of ITRM940544A0 publication Critical patent/ITRM940544A0/it
Priority to EP95830366A priority patent/EP0698920A3/en
Priority to JP7216184A priority patent/JPH08172254A/ja
Publication of ITRM940544A1 publication Critical patent/ITRM940544A1/it
Application granted granted Critical
Publication of IT1272817B publication Critical patent/IT1272817B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H10W70/415—Leadframe inner leads serving as die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/865—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

Procedimento per il montaggio di circuiti integrati o chip realizzati in tecnica LOC (Lead - On - Chip), aventi piazzole di connessione (11) in posizione centrale allineate lungo l'asse longitudinale, su pannelli di circuiti stampati (12) predisposti con asole allungate passanti (13) corrispondenti alla successione delle piazzole di connessione del chip, caratterizzato dal fatto di comprendere le seguenti fasi operative fondamentali:i. applicare sulla faccia inferiore del pannello di circuito stampato (12) ai lati di dette asole (13) almeno una striscia (14, 15) di un nastro biadesivo termoplastico,ii. incollare il chip (10) al pannello (12) tramite dette strisce (14, 15) di nastro biadesivo termoplastico,iii. connettere le singole piazzole di contatto (11) del chip alle corrispondenti piazzole di contatto del circuito stampato attraverso dette asole (13) ed eseguire i collaudi elettrici e funzionali,iv. applicare una copertura di incapsulamento di resina protettiva (16) sulla faccia superiore del pannello di circuito stampato (12), nell'asola (13) e sui relativi collegamenti (18) effettuati attraverso di essa,v. applicare una copertura di incapsulamento di resina protettiva (17) sulla faccia inferiore del pannello di circuito stampato (12) in modo da inglobare l'intero chip (10),vi. polimerizzare in forno detti incapsulamenti di resina protettiva (16, 17).
ITRM940544A 1994-08-24 1994-08-24 Procedimento per il montaggio di circuiti integrati su pannelli di circuiti stampati IT1272817B (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
ITRM940544A IT1272817B (it) 1994-08-24 1994-08-24 Procedimento per il montaggio di circuiti integrati su pannelli di circuiti stampati
EP95830366A EP0698920A3 (en) 1994-08-24 1995-08-24 A method for assembling integrated circuits upon printed circuit boards
JP7216184A JPH08172254A (ja) 1994-08-24 1995-08-24 集積回路の組立法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ITRM940544A IT1272817B (it) 1994-08-24 1994-08-24 Procedimento per il montaggio di circuiti integrati su pannelli di circuiti stampati

Publications (3)

Publication Number Publication Date
ITRM940544A0 ITRM940544A0 (it) 1994-08-24
ITRM940544A1 ITRM940544A1 (it) 1996-02-24
IT1272817B true IT1272817B (it) 1997-06-30

Family

ID=11402704

Family Applications (1)

Application Number Title Priority Date Filing Date
ITRM940544A IT1272817B (it) 1994-08-24 1994-08-24 Procedimento per il montaggio di circuiti integrati su pannelli di circuiti stampati

Country Status (3)

Country Link
EP (1) EP0698920A3 (it)
JP (1) JPH08172254A (it)
IT (1) IT1272817B (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6667560B2 (en) * 1996-05-29 2003-12-23 Texas Instruments Incorporated Board on chip ball grid array
US6577015B1 (en) * 2000-03-07 2003-06-10 Micron Technology, Inc. Partial slot cover for encapsulation process
JP2023139563A (ja) * 2022-03-22 2023-10-04 日本無線株式会社 マルチチップモジュール

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58178529A (ja) * 1982-04-13 1983-10-19 Mitsubishi Electric Corp 混成集積回路装置
DE3911711A1 (de) * 1989-04-10 1990-10-11 Ibm Modul-aufbau mit integriertem halbleiterchip und chiptraeger
US5227232A (en) * 1991-01-23 1993-07-13 Lim Thiam B Conductive tape for semiconductor package, a lead frame without power buses for lead on chip package, and a semiconductor device with conductive tape power distribution
US5384689A (en) * 1993-12-20 1995-01-24 Shen; Ming-Tung Integrated circuit chip including superimposed upper and lower printed circuit boards

Also Published As

Publication number Publication date
ITRM940544A1 (it) 1996-02-24
JPH08172254A (ja) 1996-07-02
ITRM940544A0 (it) 1994-08-24
EP0698920A3 (en) 1998-01-07
EP0698920A2 (en) 1996-02-28

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