IT1284718B1 - Dispositivo e procedimento per allineare temporalmente segnali numerici, ad esempio un segnale di orologio ed un flusso di dati. - Google Patents

Dispositivo e procedimento per allineare temporalmente segnali numerici, ad esempio un segnale di orologio ed un flusso di dati.

Info

Publication number
IT1284718B1
IT1284718B1 IT96TO000665A ITTO960665A IT1284718B1 IT 1284718 B1 IT1284718 B1 IT 1284718B1 IT 96TO000665 A IT96TO000665 A IT 96TO000665A IT TO960665 A ITTO960665 A IT TO960665A IT 1284718 B1 IT1284718 B1 IT 1284718B1
Authority
IT
Italy
Prior art keywords
procedure
flow
data
clock signal
numerical signals
Prior art date
Application number
IT96TO000665A
Other languages
English (en)
Inventor
Bruno Bostica
Marco Burzio
Paolo Pellegrino
Original Assignee
Cselt Centro Studi Lab Telecom
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cselt Centro Studi Lab Telecom filed Critical Cselt Centro Studi Lab Telecom
Priority to IT96TO000665A priority Critical patent/IT1284718B1/it
Priority to US08/869,936 priority patent/US6067334A/en
Priority to JP21547897A priority patent/JP3217017B2/ja
Priority to EP97113112A priority patent/EP0822683B1/en
Priority to CA002212292A priority patent/CA2212292C/en
Priority to DE69734954T priority patent/DE69734954T2/de
Publication of ITTO960665A1 publication Critical patent/ITTO960665A1/it
Application granted granted Critical
Publication of IT1284718B1 publication Critical patent/IT1284718B1/it

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Communication Control (AREA)
IT96TO000665A 1996-07-31 1996-07-31 Dispositivo e procedimento per allineare temporalmente segnali numerici, ad esempio un segnale di orologio ed un flusso di dati. IT1284718B1 (it)

Priority Applications (6)

Application Number Priority Date Filing Date Title
IT96TO000665A IT1284718B1 (it) 1996-07-31 1996-07-31 Dispositivo e procedimento per allineare temporalmente segnali numerici, ad esempio un segnale di orologio ed un flusso di dati.
US08/869,936 US6067334A (en) 1996-07-31 1997-06-05 Device for and method of aligning in time digital signals, for example a clock signal and data stream
JP21547897A JP3217017B2 (ja) 1996-07-31 1997-07-28 クロック信号やデータストリームのようなデジタル信号を時間整列するための装置及び方法
EP97113112A EP0822683B1 (en) 1996-07-31 1997-07-30 Device for and method of aligning in time digital signals, for example a clock signal and a data stream
CA002212292A CA2212292C (en) 1996-07-31 1997-07-30 Device for and method of aligning in time digital signals, for example a clock signal and a data stream
DE69734954T DE69734954T2 (de) 1996-07-31 1997-07-30 Verfahren und Vorrichtung zur Einphasung von digitalen Zeitsignalen wie z.B. einem Taktsignal und einem Datenstrom

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT96TO000665A IT1284718B1 (it) 1996-07-31 1996-07-31 Dispositivo e procedimento per allineare temporalmente segnali numerici, ad esempio un segnale di orologio ed un flusso di dati.

Publications (2)

Publication Number Publication Date
ITTO960665A1 ITTO960665A1 (it) 1998-01-31
IT1284718B1 true IT1284718B1 (it) 1998-05-21

Family

ID=11414832

Family Applications (1)

Application Number Title Priority Date Filing Date
IT96TO000665A IT1284718B1 (it) 1996-07-31 1996-07-31 Dispositivo e procedimento per allineare temporalmente segnali numerici, ad esempio un segnale di orologio ed un flusso di dati.

Country Status (6)

Country Link
US (1) US6067334A (it)
EP (1) EP0822683B1 (it)
JP (1) JP3217017B2 (it)
CA (1) CA2212292C (it)
DE (1) DE69734954T2 (it)
IT (1) IT1284718B1 (it)

Families Citing this family (20)

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Publication number Priority date Publication date Assignee Title
JPH10328163A (ja) 1997-05-28 1998-12-15 Siemens Ag 核スピン断層撮影装置のためのパルスシーケンスの制御方法及び装置
US6502123B1 (en) 1998-06-09 2002-12-31 Advanced Micro Devices, Inc. Isochronous system using certified drivers to ensure system stability
US6421702B1 (en) * 1998-06-09 2002-07-16 Advanced Micro Devices, Inc. Interrupt driven isochronous task scheduler system
US6704763B1 (en) 1998-06-09 2004-03-09 Advanced Micro Devices, Inc. Hardware enforcement mechanism for an isochronous task scheduler
US6400706B1 (en) * 1999-04-02 2002-06-04 Qualcomm Incorporated System and method for re-synchronizing a phase-independent first-in first-out memory
EP1076435A1 (en) * 1999-08-12 2001-02-14 STMicroelectronics S.r.l. A detector for detecting timing in a data flow
US6333653B1 (en) * 1999-11-04 2001-12-25 International Business Machines Corporation System and method for phase alignment of a plurality of clock pulses when starting, stopping and pulsing clocks
EP1172962A3 (en) * 2000-07-13 2003-09-03 Tektronix, Inc. Bit rate agile clock recovery circuit
US8385476B2 (en) 2001-04-25 2013-02-26 Texas Instruments Incorporated Digital phase locked loop
EP1331750A1 (en) * 2002-01-28 2003-07-30 Lucent Technologies Inc. Method and circuit arrangement for clock recovery
WO2004105303A1 (en) 2003-04-29 2004-12-02 Telefonaktiebolaget Lm Ericsson (Publ) Multiphase clock recovery
TWI243980B (en) * 2003-10-09 2005-11-21 Via Tech Inc Switch circuit for switching clock signals
US7707312B2 (en) * 2003-12-31 2010-04-27 Alcatel Lucent Printer discovery protocol system and method
US7554372B1 (en) * 2005-08-14 2009-06-30 National Semiconductor Corporation Digital dead-time controller for pulse width modulators
CN100405252C (zh) * 2005-11-11 2008-07-23 鸿富锦精密工业（深圳）有限公司 时钟信号转换电路
US7816960B2 (en) * 2007-08-09 2010-10-19 Qualcomm Incorporated Circuit device and method of measuring clock jitter
US9281934B2 (en) * 2014-05-02 2016-03-08 Qualcomm Incorporated Clock and data recovery with high jitter tolerance and fast phase locking
US10158364B1 (en) * 2017-08-31 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Realignment strength controller for solving loop conflict of realignment phase lock loop
PL3560144T3 (pl) 2018-12-21 2021-10-25 Advanced New Technologies Co., Ltd. Ochrona danych łańcucha bloków oparta na ogólnym modelu konta i szyfrowaniu homomorficznym
EP3566197B1 (en) 2018-12-21 2022-03-30 Advanced New Technologies Co., Ltd. Blockchain data protection based on generic account model and homomorphic encryption

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4672639A (en) * 1984-05-24 1987-06-09 Kabushiki Kaisha Toshiba Sampling clock pulse generator
US4700347A (en) * 1985-02-13 1987-10-13 Bolt Beranek And Newman Inc. Digital phase adjustment
FR2604043B1 (fr) * 1986-09-17 1993-04-09 Cit Alcatel Dispositif de recalage d'un ou plusieurs trains de donnees binaires de debits identiques ou sous-multiples sur un signal de reference d'horloge synchrone
US5022057A (en) * 1988-03-11 1991-06-04 Hitachi, Ltd. Bit synchronization circuit
US5034967A (en) * 1988-11-14 1991-07-23 Datapoint Corporation Metastable-free digital synchronizer with low phase error
ATE110505T1 (de) * 1989-02-23 1994-09-15 Siemens Ag Verfahren und anordnung zum anpassen eines taktes an ein plesiochrones datensignal und zu dessen abtakten mit dem angepassten takt.
US5022056A (en) * 1989-10-23 1991-06-04 National Semiconductor Corporation Method and structure for digital phase synchronization
JPH0778774B2 (ja) * 1991-02-22 1995-08-23 インターナショナル・ビジネス・マシーンズ・コーポレイション 短待ち時間データ回復装置及びメッセージデータの同期化方法
DE69332333T2 (de) * 1993-10-12 2003-05-15 Alcatel, Paris Synchronisierungsschaltung
US5689530A (en) * 1994-06-22 1997-11-18 Alcatel Network Systems, Inc. Data recovery circuit with large retime margin

Also Published As

Publication number Publication date
EP0822683B1 (en) 2005-12-28
US6067334A (en) 2000-05-23
EP0822683A2 (en) 1998-02-04
DE69734954T2 (de) 2006-08-24
JPH1091578A (ja) 1998-04-10
CA2212292C (en) 2001-10-16
CA2212292A1 (en) 1998-01-31
EP0822683A3 (en) 2000-11-08
DE69734954D1 (de) 2006-02-02
JP3217017B2 (ja) 2001-10-09
ITTO960665A1 (it) 1998-01-31

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Legal Events

Date Code Title Description
0001 Granted