IT7920675A0 - Processo per la formazione di conduttori e fori subminiatura eprodotto ottenuto con l'ausilio ditale processo. - Google Patents

Processo per la formazione di conduttori e fori subminiatura eprodotto ottenuto con l'ausilio ditale processo.

Info

Publication number
IT7920675A0
IT7920675A0 IT7920675A IT2067579A IT7920675A0 IT 7920675 A0 IT7920675 A0 IT 7920675A0 IT 7920675 A IT7920675 A IT 7920675A IT 2067579 A IT2067579 A IT 2067579A IT 7920675 A0 IT7920675 A0 IT 7920675A0
Authority
IT
Italy
Prior art keywords
subminiature
conductors
aid
formation
holes
Prior art date
Application number
IT7920675A
Other languages
English (en)
Other versions
IT1202900B (it
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Publication of IT7920675A0 publication Critical patent/IT7920675A0/it
Application granted granted Critical
Publication of IT1202900B publication Critical patent/IT1202900B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/80—Material per se process of making same
    • Y10S505/815—Process of making per se
    • Y10S505/816—Sputtering, including coating, forming, or etching
IT20675/79A 1978-03-02 1979-03-01 Processo per la formazione di conduttori e fori subminiatura e prodotto ottenuto con l'ausilio di tale processo IT1202900B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/882,826 US4176029A (en) 1978-03-02 1978-03-02 Subminiature bore and conductor formation

Publications (2)

Publication Number Publication Date
IT7920675A0 true IT7920675A0 (it) 1979-03-01
IT1202900B IT1202900B (it) 1989-02-15

Family

ID=25381412

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20675/79A IT1202900B (it) 1978-03-02 1979-03-01 Processo per la formazione di conduttori e fori subminiatura e prodotto ottenuto con l'ausilio di tale processo

Country Status (5)

Country Link
US (1) US4176029A (it)
EP (1) EP0004164B1 (it)
JP (1) JPS54125996A (it)
DE (1) DE2964037D1 (it)
IT (1) IT1202900B (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4263603A (en) * 1978-03-02 1981-04-21 Sperry Corporation Subminiature bore and conductor formation
JPS56150883A (en) * 1979-12-25 1981-11-21 Nippon Telegr & Teleph Corp <Ntt> Josephson switching element
US4430790A (en) * 1980-05-20 1984-02-14 Rikagaku Kenkyusho Method of making a Josephson junction
US4370359A (en) * 1980-08-18 1983-01-25 Bell Telephone Laboratories, Incorporated Fabrication technique for junction devices
US4592132A (en) * 1984-12-07 1986-06-03 Hughes Aircraft Company Process for fabricating multi-level-metal integrated circuits at high yields
WO1995028000A2 (en) * 1994-04-07 1995-10-19 Philips Electronics N.V. Method of manufacturing a semiconductor device with a multilayer wiring structure containing narrow vias
US6331680B1 (en) 1996-08-07 2001-12-18 Visteon Global Technologies, Inc. Multilayer electrical interconnection device and method of making same
US7615385B2 (en) 2006-09-20 2009-11-10 Hypres, Inc Double-masking technique for increasing fabrication yield in superconducting electronics
JP6254032B2 (ja) * 2014-03-28 2017-12-27 住友重機械工業株式会社 Ｓｎｓ型ジョセフソン接合素子の製造方法及びｓｎｓ型ジョセフソン接合素子製造装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3588777A (en) * 1968-07-15 1971-06-28 Texas Instruments Inc Superconducting tunneling barriers
US3599009A (en) * 1968-07-19 1971-08-10 Wisconsin Alumni Res Found Neuristor transmission line, learning junction, and artificial neuron
US3837907A (en) * 1972-03-22 1974-09-24 Bell Telephone Labor Inc Multiple-level metallization for integrated circuits
DE2459663C2 (de) * 1974-12-17 1977-01-13 Siemens Ag Verfahren zum herstellen von supraleitfaehigen mikrobruecken
US4096508A (en) * 1975-11-14 1978-06-20 Bell Telephone Laboratories, Incorporated Multiple junction supercurrent memory device utilizing flux vortices
JPS5277695A (en) * 1975-12-24 1977-06-30 Fujitsu Ltd Josephson device
JPS5929136B2 (ja) * 1976-03-30 1984-07-18 株式会社東芝 半導体装置の製造方法
US4060427A (en) * 1976-04-05 1977-11-29 Ibm Corporation Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps
US4076575A (en) * 1976-06-30 1978-02-28 International Business Machines Corporation Integrated fabrication method of forming connectors through insulative layers
DE2629996A1 (de) * 1976-07-03 1978-01-05 Ibm Deutschland Verfahren zur passivierung und planarisierung eines metallisierungsmusters
US4055847A (en) * 1976-08-13 1977-10-25 Nasa Germanium coated microbridge and method
US4087314A (en) * 1976-09-13 1978-05-02 Motorola, Inc. Bonding pedestals for semiconductor devices
US4070501A (en) * 1976-10-28 1978-01-24 Ibm Corporation Forming self-aligned via holes in thin film interconnection systems

Also Published As

Publication number Publication date
JPS54125996A (en) 1979-09-29
EP0004164A1 (en) 1979-09-19
JPS639391B2 (it) 1988-02-29
US4176029A (en) 1979-11-27
IT1202900B (it) 1989-02-15
DE2964037D1 (en) 1982-12-23
EP0004164B1 (en) 1982-11-17

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