IT8021996A0 - Processo di fabbricazione di circuiti integrati. - Google Patents

Processo di fabbricazione di circuiti integrati.

Info

Publication number
IT8021996A0
IT8021996A0 IT8021996A IT2199680A IT8021996A0 IT 8021996 A0 IT8021996 A0 IT 8021996A0 IT 8021996 A IT8021996 A IT 8021996A IT 2199680 A IT2199680 A IT 2199680A IT 8021996 A0 IT8021996 A0 IT 8021996A0
Authority
IT
Italy
Prior art keywords
manufacturing process
integrated circuits
circuits manufacturing
integrated
manufacturing
Prior art date
Application number
IT8021996A
Other languages
English (en)
Other versions
IT1149834B (it
Inventor
Cheng Tzong Horng
Robert Otto Schwenker
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT8021996A0 publication Critical patent/IT8021996A0/it
Application granted granted Critical
Publication of IT1149834B publication Critical patent/IT1149834B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H10W10/0123—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves using auxiliary pillars in the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/05—Etch and refill
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/111—Narrow masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie
IT21996/80A 1979-06-28 1980-05-13 Processo di fabbricazione di circuiti integrati IT1149834B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/052,997 US4211582A (en) 1979-06-28 1979-06-28 Process for making large area isolation trenches utilizing a two-step selective etching technique

Publications (2)

Publication Number Publication Date
IT8021996A0 true IT8021996A0 (it) 1980-05-13
IT1149834B IT1149834B (it) 1986-12-10

Family

ID=21981249

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21996/80A IT1149834B (it) 1979-06-28 1980-05-13 Processo di fabbricazione di circuiti integrati

Country Status (6)

Country Link
US (1) US4211582A (it)
EP (1) EP0021147B1 (it)
JP (1) JPS5837987B2 (it)
CA (1) CA1139017A (it)
DE (1) DE3071381D1 (it)
IT (1) IT1149834B (it)

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US4287661A (en) * 1980-03-26 1981-09-08 International Business Machines Corporation Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation
US4378630A (en) * 1980-05-05 1983-04-05 International Business Machines Corporation Process for fabricating a high performance PNP and NPN structure
US4394196A (en) * 1980-07-16 1983-07-19 Tokyo Shibaura Denki Kabushiki Kaisha Method of etching, refilling and etching dielectric grooves for isolating micron size device regions
JPS5748237A (en) * 1980-09-05 1982-03-19 Nec Corp Manufacture of 2n doubling pattern
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US4400715A (en) * 1980-11-19 1983-08-23 International Business Machines Corporation Thin film semiconductor device and method for manufacture
US4415371A (en) * 1980-12-29 1983-11-15 Rockwell International Corporation Method of making sub-micron dimensioned NPN lateral transistor
DE3102647A1 (de) * 1981-01-27 1982-08-19 Siemens AG, 1000 Berlin und 8000 München Strukturierung von metalloxidmasken, insbesondere durch reaktives ionenstrahlaetzen
JPS57170533A (en) * 1981-04-13 1982-10-20 Nec Corp Forming method for mask pattern
GB2104287B (en) * 1981-08-21 1985-02-20 Gen Electric Co Plc Data storage devices
EP0073025B1 (en) * 1981-08-21 1989-08-09 Kabushiki Kaisha Toshiba Method of manufacturing dielectric isolation regions for a semiconductor device
US4491486A (en) * 1981-09-17 1985-01-01 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device
US4432132A (en) * 1981-12-07 1984-02-21 Bell Telephone Laboratories, Incorporated Formation of sidewall oxide layers by reactive oxygen ion etching to define submicron features
US4430791A (en) * 1981-12-30 1984-02-14 International Business Machines Corporation Sub-micrometer channel length field effect transistor process
US4385975A (en) * 1981-12-30 1983-05-31 International Business Machines Corp. Method of forming wide, deep dielectric filled isolation trenches in the surface of a silicon semiconductor substrate
US4424621A (en) 1981-12-30 1984-01-10 International Business Machines Corporation Method to fabricate stud structure for self-aligned metallization
JPS58217499A (ja) * 1982-06-10 1983-12-17 Toshiba Corp 薄膜の微細加工方法
US4444605A (en) * 1982-08-27 1984-04-24 Texas Instruments Incorporated Planar field oxide for semiconductor devices
JPS59132627A (ja) * 1983-01-20 1984-07-30 Matsushita Electronics Corp パタ−ン形成方法
US4771328A (en) * 1983-10-13 1988-09-13 International Business Machine Corporation Semiconductor device and process
USH204H (en) 1984-11-29 1987-02-03 At&T Bell Laboratories Method for implanting the sidewalls of isolation trenches
US4648173A (en) * 1985-05-28 1987-03-10 International Business Machines Corporation Fabrication of stud-defined integrated circuit structure
US4753901A (en) * 1985-11-15 1988-06-28 Ncr Corporation Two mask technique for planarized trench oxide isolation of integrated devices
US4801350A (en) * 1986-12-29 1989-01-31 Motorola, Inc. Method for obtaining submicron features from optical lithography technology
US5130268A (en) * 1991-04-05 1992-07-14 Sgs-Thomson Microelectronics, Inc. Method for forming planarized shallow trench isolation in an integrated circuit and a structure formed thereby
US5292689A (en) * 1992-09-04 1994-03-08 International Business Machines Corporation Method for planarizing semiconductor structure using subminimum features
US5290358A (en) * 1992-09-30 1994-03-01 International Business Machines Corporation Apparatus for directional low pressure chemical vapor deposition (DLPCVD)
JP3324832B2 (ja) * 1993-07-28 2002-09-17 三菱電機株式会社 半導体装置およびその製造方法
US5294562A (en) * 1993-09-27 1994-03-15 United Microelectronics Corporation Trench isolation with global planarization using flood exposure
US5372968A (en) * 1993-09-27 1994-12-13 United Microelectronics Corporation Planarized local oxidation by trench-around technology
US5308786A (en) * 1993-09-27 1994-05-03 United Microelectronics Corporation Trench isolation for both large and small areas by means of silicon nodules after metal etching
US5366925A (en) * 1993-09-27 1994-11-22 United Microelectronics Corporation Local oxidation of silicon by using aluminum spiking technology
KR960014452B1 (ko) * 1993-12-22 1996-10-15 금성일렉트론 주식회사 반도체 소자분리 방법
US5395790A (en) * 1994-05-11 1995-03-07 United Microelectronics Corp. Stress-free isolation layer
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US5904539A (en) * 1996-03-21 1999-05-18 Advanced Micro Devices, Inc. Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties
US5742090A (en) * 1996-04-04 1998-04-21 Advanced Micro Devices, Inc. Narrow width trenches for field isolation in integrated circuits
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US7723172B2 (en) * 2007-04-23 2010-05-25 Icemos Technology Ltd. Methods for manufacturing a trench type semiconductor device having a thermally sensitive refill material
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Also Published As

Publication number Publication date
US4211582A (en) 1980-07-08
EP0021147A2 (de) 1981-01-07
JPS5837987B2 (ja) 1983-08-19
EP0021147B1 (de) 1986-01-29
JPS566450A (en) 1981-01-23
IT1149834B (it) 1986-12-10
DE3071381D1 (en) 1986-03-13
EP0021147A3 (en) 1983-04-06
CA1139017A (en) 1983-01-04

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