IT8224131A0 - Unita' di memoria, di sola lettura, collegate in cascata, perl'elaborazione di segnali. - Google Patents

Unita' di memoria, di sola lettura, collegate in cascata, perl'elaborazione di segnali.

Info

Publication number
IT8224131A0
IT8224131A0 IT8224131A IT2413182A IT8224131A0 IT 8224131 A0 IT8224131 A0 IT 8224131A0 IT 8224131 A IT8224131 A IT 8224131A IT 2413182 A IT2413182 A IT 2413182A IT 8224131 A0 IT8224131 A0 IT 8224131A0
Authority
IT
Italy
Prior art keywords
cascade
read
signal processing
memory units
units
Prior art date
Application number
IT8224131A
Other languages
English (en)
Other versions
IT1163017B (it
IT8224131A1 (it
Inventor
Robert Adams Dischert
James Morgan Walter
Original Assignee
Rca Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rca Corp filed Critical Rca Corp
Publication of IT8224131A0 publication Critical patent/IT8224131A0/it
Publication of IT8224131A1 publication Critical patent/IT8224131A1/it
Application granted granted Critical
Publication of IT1163017B publication Critical patent/IT1163017B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/03—Digital function generators working, at least partly, by table look-up
    • G06F1/035—Reduction of table size
    • G06F1/0356—Reduction of table size by using two or more smaller tables, e.g. addressed by parts of the argument
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/5235—Multiplying only using indirect methods, e.g. quarter square method, via logarithmic domain
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/002—Control of digital or coded signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2101/00—Indexing scheme relating to the type of digital function generated
    • G06F2101/10—Logarithmic or exponential functions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Studio Circuits (AREA)
  • Picture Signal Circuits (AREA)
  • Processing Of Color Television Signals (AREA)
IT24131/82A 1981-11-09 1982-11-08 Unita' di memoria,di sola lettura,collegate in cascata,per l'elaborazione di segnali IT1163017B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/319,460 US4470125A (en) 1981-11-09 1981-11-09 Multiplier for digital video signals using a cascade of signal-selectable memories

Publications (3)

Publication Number Publication Date
IT8224131A0 true IT8224131A0 (it) 1982-11-08
IT8224131A1 IT8224131A1 (it) 1984-05-08
IT1163017B IT1163017B (it) 1987-04-08

Family

ID=23242334

Family Applications (1)

Application Number Title Priority Date Filing Date
IT24131/82A IT1163017B (it) 1981-11-09 1982-11-08 Unita' di memoria,di sola lettura,collegate in cascata,per l'elaborazione di segnali

Country Status (9)

Country Link
US (1) US4470125A (it)
KR (1) KR840002797A (it)
AU (1) AU554210B2 (it)
CA (1) CA1177174A (it)
DE (1) DE3241204A1 (it)
ES (1) ES517028A0 (it)
FR (1) FR2516330A1 (it)
GB (1) GB2109135B (it)
IT (1) IT1163017B (it)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4636973A (en) * 1982-07-21 1987-01-13 Raytheon Company Vernier addressing apparatus
US4599640A (en) * 1984-02-29 1986-07-08 Rca Corporation Television camera with multiplexed A-D converter
GB2155669A (en) * 1984-03-06 1985-09-25 Sony Corp Galois field multipliers
US4588986A (en) * 1984-09-28 1986-05-13 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Method and apparatus for operating on companded PCM voice data
GB8432552D0 (en) * 1984-12-21 1985-02-06 Plessey Co Plc Control circuits
JP2751927B2 (ja) * 1985-04-12 1998-05-18 アムペツクス コ−ポレ−シヨン ビデオ特殊効果生成装置
US4688095A (en) * 1986-02-07 1987-08-18 Image Technology Incorporated Programmable image-transformation system

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB839241A (en) * 1955-08-19 1960-06-29 Internat Computers & Tabulator Improvements in or relating to electronic calculating apparatus
US3443079A (en) * 1963-09-12 1969-05-06 Amos Nathan Cascade multiplier
GB1291223A (en) * 1968-10-09 1972-10-04 Nat Res Dev Digital electric circuit arrangements including shift stages
US4181970A (en) * 1973-10-08 1980-01-01 Nippon Telegraph And Telephone Public Corporation Digital attenuator for compressed PCM signals
US4118785A (en) * 1973-10-08 1978-10-03 Nippon Telegraph And Telephone Public Corporation Method and apparatus for digital attenuation by pattern shifting
US3919535A (en) * 1974-08-21 1975-11-11 Singer Co Multiple addend adder and multiplier
US4021652A (en) * 1975-12-11 1977-05-03 Northern Electric Company Limited Incrementally adjustable digital attenuator/amplifier
BE844199A (nl) * 1976-07-16 1976-11-16 Inrichting voor het vermenigvuldigen van binaire getallen
US4240106A (en) * 1976-10-14 1980-12-16 Micro Consultants, Limited Video noise reduction
US4240113A (en) * 1976-10-14 1980-12-16 Micro Consultants, Limited Picture manipulation in video systems
US4129417A (en) * 1977-10-28 1978-12-12 Miles Laboratories, Inc. Multisystem test means
US4168530A (en) * 1978-02-13 1979-09-18 Burroughs Corporation Multiplication circuit using column compression
GB2102651B (en) * 1978-03-08 1983-06-02 Tokyo Broadcasting Syst Noise reduction system for color television signal
JPS5552575A (en) * 1978-10-05 1980-04-17 Teac Co Display unit for operation state
FR2468917A1 (fr) * 1979-08-30 1981-05-08 Thomson Csf Mat Tel Dispositif variateur de niveau pour signaux numeriques
GB2059123B (en) * 1979-09-22 1983-09-21 Kokusai Denshin Denwa Co Ltd Pcm signal calculator
US4344151A (en) * 1980-04-21 1982-08-10 Rockwell International Corporation ROM-Based complex multiplier useful for FFT butterfly arithmetic unit

Also Published As

Publication number Publication date
US4470125A (en) 1984-09-04
KR840002797A (ko) 1984-07-16
IT1163017B (it) 1987-04-08
AU554210B2 (en) 1986-08-14
GB2109135A (en) 1983-05-25
FR2516330A1 (fr) 1983-05-13
DE3241204A1 (de) 1983-05-19
GB2109135B (en) 1985-04-17
ES8403264A1 (es) 1984-03-01
ES517028A0 (es) 1984-03-01
AU9010982A (en) 1983-05-19
IT8224131A1 (it) 1984-05-08
CA1177174A (en) 1984-10-30

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