IT8548045A1 - Procedimento per la formazione di contatti fra strati di polisilicioe dispositivo e semiconduttore incorporante tali contatti - Google Patents

Procedimento per la formazione di contatti fra strati di polisilicioe dispositivo e semiconduttore incorporante tali contatti

Info

Publication number
IT8548045A1
IT8548045A1 IT1985A48045A IT4804585A IT8548045A1 IT 8548045 A1 IT8548045 A1 IT 8548045A1 IT 1985A48045 A IT1985A48045 A IT 1985A48045A IT 4804585 A IT4804585 A IT 4804585A IT 8548045 A1 IT8548045 A1 IT 8548045A1
Authority
IT
Italy
Prior art keywords
contacts
polyysilicon
layers
procedure
formation
Prior art date
Application number
IT1985A48045A
Other languages
English (en)
Other versions
IT8548045A0 (it
IT1181655B (it
Original Assignee
Soc Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soc Motorola Inc filed Critical Soc Motorola Inc
Publication of IT8548045A0 publication Critical patent/IT8548045A0/it
Publication of IT8548045A1 publication Critical patent/IT8548045A1/it
Application granted granted Critical
Publication of IT1181655B publication Critical patent/IT1181655B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0114—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors to diamond, semiconducting diamond-like carbon or graphene
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H10W20/066—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by forming silicides of refractory metals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/019—Contacts of silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/164—Three dimensional processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
IT48045/85A 1984-05-24 1985-05-06 Procedimento per la formazione di contatti fra strati di polisilicio e dispositivo a semiconduttore incorporante tali contatti IT1181655B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/613,549 US4581623A (en) 1984-05-24 1984-05-24 Interlayer contact for use in a static RAM cell

Publications (3)

Publication Number Publication Date
IT8548045A0 IT8548045A0 (it) 1985-05-06
IT8548045A1 true IT8548045A1 (it) 1986-11-06
IT1181655B IT1181655B (it) 1987-09-30

Family

ID=24457737

Family Applications (1)

Application Number Title Priority Date Filing Date
IT48045/85A IT1181655B (it) 1984-05-24 1985-05-06 Procedimento per la formazione di contatti fra strati di polisilicio e dispositivo a semiconduttore incorporante tali contatti

Country Status (4)

Country Link
US (1) US4581623A (it)
EP (1) EP0189423A1 (it)
IT (1) IT1181655B (it)
WO (1) WO1985005495A1 (it)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5061986A (en) * 1985-01-22 1991-10-29 National Semiconductor Corporation Self-aligned extended base contact for a bipolar transistor having reduced cell size and improved electrical characteristics
US5045916A (en) * 1985-01-22 1991-09-03 Fairchild Semiconductor Corporation Extended silicide and external contact technology
US5227316A (en) * 1985-01-22 1993-07-13 National Semiconductor Corporation Method of forming self aligned extended base contact for a bipolar transistor having reduced cell size
DE3683679D1 (de) * 1985-04-26 1992-03-12 Fujitsu Ltd Verfahren zur herstellung einer kontaktanordnung fuer eine halbleiteranordnung.
US4975756A (en) * 1985-05-01 1990-12-04 Texas Instruments Incorporated SRAM with local interconnect
US4823314A (en) * 1985-12-13 1989-04-18 Intel Corporation Integrated circuit dual port static memory cell
JPS62260340A (ja) * 1986-05-06 1987-11-12 Toshiba Corp 半導体装置の製造方法
US4983544A (en) * 1986-10-20 1991-01-08 International Business Machines Corporation Silicide bridge contact process
KR900008868B1 (ko) * 1987-09-30 1990-12-11 삼성전자 주식회사 저항성 접촉을 갖는 반도체 장치의 제조방법
WO1989011733A1 (en) * 1988-05-24 1989-11-30 Micron Technology, Inc. Alpha shielded tisi2 local interconnects
US5801396A (en) * 1989-01-18 1998-09-01 Stmicroelectronics, Inc. Inverted field-effect device with polycrystalline silicon/germanium channel
US5770892A (en) * 1989-01-18 1998-06-23 Sgs-Thomson Microelectronics, Inc. Field effect device with polycrystalline silicon channel
US5059554A (en) * 1989-06-23 1991-10-22 Sgs-Thomson Microelectronics, Inc. Method for forming polycrystalline silicon contacts
US5288666A (en) * 1990-03-21 1994-02-22 Ncr Corporation Process for forming self-aligned titanium silicide by heating in an oxygen rich environment
US5151387A (en) * 1990-04-30 1992-09-29 Sgs-Thomson Microelectronics, Inc. Polycrystalline silicon contact structure
US5068201A (en) * 1990-05-31 1991-11-26 Sgs-Thomson Microelectronics, Inc. Method for forming a high valued resistive load element and low resistance interconnect for integrated circuits
JPH0490514A (ja) * 1990-08-02 1992-03-24 Semiconductor Energy Lab Co Ltd 半導体装置
US5204279A (en) * 1991-06-03 1993-04-20 Sgs-Thomson Microelectronics, Inc. Method of making SRAM cell and structure with polycrystalline p-channel load devices
US5462894A (en) * 1991-08-06 1995-10-31 Sgs-Thomson Microelectronics, Inc. Method for fabricating a polycrystalline silicon resistive load element in an integrated circuit
US5591674A (en) * 1991-12-30 1997-01-07 Lucent Technologies Inc. Integrated circuit with silicon contact to silicide
US5286663A (en) * 1992-01-29 1994-02-15 Micron Technology, Inc. Methods for producing thin film transistor having a diode shunt
EP0565231A3 (en) * 1992-03-31 1996-11-20 Sgs Thomson Microelectronics Method of fabricating a polysilicon thin film transistor
US5334861A (en) * 1992-05-19 1994-08-02 Motorola Inc. Semiconductor memory cell
US5232863A (en) * 1992-10-20 1993-08-03 Micron Semiconductor, Inc. Method of forming electrical contact between a field effect transistor gate and a remote active area
US20040178446A1 (en) * 1994-02-09 2004-09-16 Ravishankar Sundaresan Method of forming asymmetrical polysilicon thin film transistor
US5405806A (en) * 1994-03-29 1995-04-11 Motorola Inc. Method for forming a metal silicide interconnect in an integrated circuit
KR0136931B1 (ko) * 1994-05-12 1998-04-24 문정환 박막 트랜지스터의 구조 및 제조방법
US6140684A (en) * 1997-06-24 2000-10-31 Stmicroelectronic, Inc. SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers
US6110822A (en) * 1998-03-25 2000-08-29 Taiwan Semiconductor Manufacturing Company Method for forming a polysilicon-interconnect contact in a TFT-SRAM
US6417032B1 (en) * 2000-04-11 2002-07-09 Taiwan Semiconductor Manufacturing Company Method of forming cross strapped Vss layout for full CMOS SRAM cell

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4398335A (en) * 1980-12-09 1983-08-16 Fairchild Camera & Instrument Corporation Multilayer metal silicide interconnections for integrated circuits
US4467518A (en) * 1981-05-19 1984-08-28 Ibm Corporation Process for fabrication of stacked, complementary MOS field effect transistor circuits
US4378628A (en) * 1981-08-27 1983-04-05 Bell Telephone Laboratories, Incorporated Cobalt silicide metallization for semiconductor integrated circuits

Also Published As

Publication number Publication date
WO1985005495A1 (en) 1985-12-05
IT8548045A0 (it) 1985-05-06
IT1181655B (it) 1987-09-30
US4581623A (en) 1986-04-08
EP0189423A1 (en) 1986-08-06

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Effective date: 19940720