IT8620460A1 - Procedimento per la realizzazione dell'isolamento di circuiti integrati a elevatissima scala d'integrazione, in particolare in tecnologia mos e cmos - Google Patents

Procedimento per la realizzazione dell'isolamento di circuiti integrati a elevatissima scala d'integrazione, in particolare in tecnologia mos e cmos

Info

Publication number
IT8620460A1
IT8620460A1 IT1986A20460A IT2046086A IT8620460A1 IT 8620460 A1 IT8620460 A1 IT 8620460A1 IT 1986A20460 A IT1986A20460 A IT 1986A20460A IT 2046086 A IT2046086 A IT 2046086A IT 8620460 A1 IT8620460 A1 IT 8620460A1
Authority
IT
Italy
Prior art keywords
mos
realization
insulation
procedure
integrated circuits
Prior art date
Application number
IT1986A20460A
Other languages
English (en)
Other versions
IT1189143B (it
IT8620460A0 (it
Original Assignee
Sgs Microelettronica Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Microelettronica Spa filed Critical Sgs Microelettronica Spa
Priority to IT20460/86A priority Critical patent/IT1189143B/it
Publication of IT8620460A0 publication Critical patent/IT8620460A0/it
Priority to EP87106645A priority patent/EP0245783A3/en
Priority to JP62119957A priority patent/JPS62285440A/ja
Publication of IT8620460A1 publication Critical patent/IT8620460A1/it
Application granted granted Critical
Publication of IT1189143B publication Critical patent/IT1189143B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/041—Manufacture or treatment of isolation regions comprising polycrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H10W10/0147—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape the shapes being altered by a local oxidation of silicon process, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/40—Isolation regions comprising polycrystalline semiconductor materials
IT20460/86A 1986-05-16 1986-05-16 Procedimento per la realizzazione dell'isolamento di circuiti integrati a elevatissima scala d'integrazione,in particolare in tecnologia mos e cmos IT1189143B (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT20460/86A IT1189143B (it) 1986-05-16 1986-05-16 Procedimento per la realizzazione dell'isolamento di circuiti integrati a elevatissima scala d'integrazione,in particolare in tecnologia mos e cmos
EP87106645A EP0245783A3 (en) 1986-05-16 1987-05-07 Insulation method for integrated circuits, in particular with mos and cmos devices
JP62119957A JPS62285440A (ja) 1986-05-16 1987-05-15 集積回路のための絶縁方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT20460/86A IT1189143B (it) 1986-05-16 1986-05-16 Procedimento per la realizzazione dell'isolamento di circuiti integrati a elevatissima scala d'integrazione,in particolare in tecnologia mos e cmos

Publications (3)

Publication Number Publication Date
IT8620460A0 IT8620460A0 (it) 1986-05-16
IT8620460A1 true IT8620460A1 (it) 1987-11-16
IT1189143B IT1189143B (it) 1988-01-28

Family

ID=11167280

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20460/86A IT1189143B (it) 1986-05-16 1986-05-16 Procedimento per la realizzazione dell'isolamento di circuiti integrati a elevatissima scala d'integrazione,in particolare in tecnologia mos e cmos

Country Status (3)

Country Link
EP (1) EP0245783A3 (it)
JP (1) JPS62285440A (it)
IT (1) IT1189143B (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01185936A (ja) * 1988-01-21 1989-07-25 Fujitsu Ltd 半導体装置
JPH05109762A (ja) * 1991-05-16 1993-04-30 Internatl Business Mach Corp <Ibm> 半導体装置及びその製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4238278A (en) * 1979-06-14 1980-12-09 International Business Machines Corporation Polycrystalline silicon oxidation method for making shallow and deep isolation trenches
JPS5958838A (ja) * 1982-09-29 1984-04-04 Hitachi Ltd 半導体装置
FR2598557B1 (fr) * 1986-05-09 1990-03-30 Seiko Epson Corp Procede de fabrication d'une region d'isolation d'element d'un dispositif a semi-conducteurs

Also Published As

Publication number Publication date
EP0245783A2 (en) 1987-11-19
JPS62285440A (ja) 1987-12-11
IT1189143B (it) 1988-01-28
IT8620460A0 (it) 1986-05-16
EP0245783A3 (en) 1989-10-25

Similar Documents

Publication Publication Date Title
EP0254212A3 (en) Mos semiconductor circuit
EP0242623A3 (en) Mos semiconductor device and method of manufacturing the same
KR910016236A (ko) 반도체 집적회로
GB2198285B (en) Bipolar transistor and method of manufacturing the same
DE3774253D1 (de) Spannungsschalter in mos-technologie.
DE3666753D1 (en) Integrated semiconductor structure and fabrication method
IT1190325B (it) Circuito di polarizzazione per dispositivi integrati in tecnologia mos,particolarmente di tipo misto digitale-analogico
DE3686310D1 (de) Dielektrisch isoliertes integriertes halbleiterbauelement und herstellungsverfahren.
KR900008651B1 (en) Bipolar transistor and the manufacturing method
GB2168534B (en) Integrated power mos bridge circuit and method
IT1185638B (it) Amplificatore operazionale tutto differenziale per circuiti integrati in tecnologia mos
ITTO910929A0 (it) Procedimento per la fabbricazione di circuiti integrati in tecnologia mos
GB2168842B (en) Integrated semiconductor power devices
KR860005412A (ko) 스위치 웨이퍼의 제법 및 그 웨이퍼
DE3583113D1 (de) Integrierte halbleiterschaltungsanordnung in polycell-technik.
DE3278605D1 (en) Intermediate structure for use in the manufacture of semiconductor devices, method of making field effect transistors and transistors
GB2168845B (en) Bipolar transistor integrated circuit and method of manufacturing the same
DE3774737D1 (de) Abschaltbares halbleiterbauelement sowie verwendung desselben.
EP0273047A4 (en) BIDIRECTIONAL VERTICAL FEED MOS DEVICE AND MANUFACTURING METHOD.
IT8767440A0 (it) Sommatore veloce in tecnologia c mos
KR860005445A (ko) Mos형 집적회로
FR2568723B1 (fr) Circuit integre notamment de type mos et son procede de fabrication
IT1189143B (it) Procedimento per la realizzazione dell&#39;isolamento di circuiti integrati a elevatissima scala d&#39;integrazione,in particolare in tecnologia mos e cmos
IT8620660A0 (it) Generatore di polarizzazione di sorgenti per transistori naturali in circuiti integrati digitali in tecnologia mos.
IT1224656B (it) Procedimento per la fabbricazione di condensatori integrati in tecnologia mos.

Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970530