IT8622853A0 - Procedimento per la fabbricazione di dispositivi cmos con riduzione del numero di fasi di mascheratura. - Google Patents

Procedimento per la fabbricazione di dispositivi cmos con riduzione del numero di fasi di mascheratura.

Info

Publication number
IT8622853A0
IT8622853A0 IT8622853A IT2285386A IT8622853A0 IT 8622853 A0 IT8622853 A0 IT 8622853A0 IT 8622853 A IT8622853 A IT 8622853A IT 2285386 A IT2285386 A IT 2285386A IT 8622853 A0 IT8622853 A0 IT 8622853A0
Authority
IT
Italy
Prior art keywords
procedure
manufacture
reduction
cmos devices
masking
Prior art date
Application number
IT8622853A
Other languages
English (en)
Other versions
IT1200578B (it
Inventor
Stefano Mazzali
Original Assignee
Sgs Microelettronica Spa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sgs Microelettronica Spa filed Critical Sgs Microelettronica Spa
Priority to IT22853/86A priority Critical patent/IT1200578B/it
Publication of IT8622853A0 publication Critical patent/IT8622853A0/it
Priority to EP87118793A priority patent/EP0275508A1/en
Priority to JP62326641A priority patent/JPS63232457A/ja
Application granted granted Critical
Publication of IT1200578B publication Critical patent/IT1200578B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H10W10/0127—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers using both n-type and p-type impurities, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
IT22853/86A 1986-12-23 1986-12-23 Procedimento per la fabbricazione di dispositivi cmos con riduzione del numero di fasi di mascheratura IT1200578B (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT22853/86A IT1200578B (it) 1986-12-23 1986-12-23 Procedimento per la fabbricazione di dispositivi cmos con riduzione del numero di fasi di mascheratura
EP87118793A EP0275508A1 (en) 1986-12-23 1987-12-18 Method for making CMOS devices
JP62326641A JPS63232457A (ja) 1986-12-23 1987-12-22 相補形金属酸化膜半導体デバイスを製造するための方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT22853/86A IT1200578B (it) 1986-12-23 1986-12-23 Procedimento per la fabbricazione di dispositivi cmos con riduzione del numero di fasi di mascheratura

Publications (2)

Publication Number Publication Date
IT8622853A0 true IT8622853A0 (it) 1986-12-23
IT1200578B IT1200578B (it) 1989-01-27

Family

ID=11201192

Family Applications (1)

Application Number Title Priority Date Filing Date
IT22853/86A IT1200578B (it) 1986-12-23 1986-12-23 Procedimento per la fabbricazione di dispositivi cmos con riduzione del numero di fasi di mascheratura

Country Status (3)

Country Link
EP (1) EP0275508A1 (it)
JP (1) JPS63232457A (it)
IT (1) IT1200578B (it)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4925806A (en) * 1988-03-17 1990-05-15 Northern Telecom Limited Method for making a doped well in a semiconductor substrate
JPH05267604A (ja) * 1991-05-08 1993-10-15 Seiko Instr Inc 半導体装置の製造方法
EP0637074A3 (en) 1993-07-30 1995-06-21 Sgs Thomson Microelectronics Process for the production of active and isolated areas by split imaging.
TW301027B (it) * 1994-11-28 1997-03-21 Advanced Micro Devices Inc

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5766659A (en) * 1980-10-09 1982-04-22 Toshiba Corp Manufacture of complementary mos semiconductor device
JPS6144456A (ja) * 1984-08-09 1986-03-04 Fujitsu Ltd 半導体装置の製造方法
JPS6165471A (ja) * 1984-09-07 1986-04-04 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0275508A1 (en) 1988-07-27
JPS63232457A (ja) 1988-09-28
IT1200578B (it) 1989-01-27

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19961227