IT8648206A0 - Struttura multistrato di fotopolimero per la realizzazione di un doppio incasso autoallineante su gaas - Google Patents

Struttura multistrato di fotopolimero per la realizzazione di un doppio incasso autoallineante su gaas

Info

Publication number
IT8648206A0
IT8648206A0 IT8648206A IT4820686A IT8648206A0 IT 8648206 A0 IT8648206 A0 IT 8648206A0 IT 8648206 A IT8648206 A IT 8648206A IT 4820686 A IT4820686 A IT 4820686A IT 8648206 A0 IT8648206 A0 IT 8648206A0
Authority
IT
Italy
Prior art keywords
recessing
gaas
aligning
creation
double self
Prior art date
Application number
IT8648206A
Other languages
English (en)
Other versions
IT1203822B (it
Inventor
Cetronio Antonio
D Eustacchio Patrizio
Moretti Sergio
Original Assignee
Selenia Ind Elettroniche
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Selenia Ind Elettroniche filed Critical Selenia Ind Elettroniche
Priority to IT48206/86A priority Critical patent/IT1203822B/it
Publication of IT8648206A0 publication Critical patent/IT8648206A0/it
Priority to EP87830242A priority patent/EP0252888A3/en
Application granted granted Critical
Publication of IT1203822B publication Critical patent/IT1203822B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/061—Manufacture or treatment of FETs having Schottky gates
    • H10D30/0612—Manufacture or treatment of FETs having Schottky gates of lateral single-gate Schottky FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • H10D30/877—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET] having recessed gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/694—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks or redeposited masks
IT48206/86A 1986-06-30 1986-06-30 Struttura multistrato di fotopolimero per la realizzazione di un doppio incasso autoallineante su gaas IT1203822B (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT48206/86A IT1203822B (it) 1986-06-30 1986-06-30 Struttura multistrato di fotopolimero per la realizzazione di un doppio incasso autoallineante su gaas
EP87830242A EP0252888A3 (en) 1986-06-30 1987-06-26 Photopolymer multilayer structure for the production of a gaas self aligning double recess

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT48206/86A IT1203822B (it) 1986-06-30 1986-06-30 Struttura multistrato di fotopolimero per la realizzazione di un doppio incasso autoallineante su gaas

Publications (2)

Publication Number Publication Date
IT8648206A0 true IT8648206A0 (it) 1986-06-30
IT1203822B IT1203822B (it) 1989-02-23

Family

ID=11265225

Family Applications (1)

Application Number Title Priority Date Filing Date
IT48206/86A IT1203822B (it) 1986-06-30 1986-06-30 Struttura multistrato di fotopolimero per la realizzazione di un doppio incasso autoallineante su gaas

Country Status (2)

Country Link
EP (1) EP0252888A3 (it)
IT (1) IT1203822B (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH023938A (ja) * 1988-06-20 1990-01-09 Mitsubishi Electric Corp 電界効果トランジスタ
JPH0828380B2 (ja) * 1989-03-03 1996-03-21 三菱電機株式会社 半導体装置の製造方法
US5139968A (en) * 1989-03-03 1992-08-18 Mitsubishi Denki Kabushiki Kaisha Method of producing a t-shaped gate electrode
US5185278A (en) * 1990-10-22 1993-02-09 Motorola, Inc. Method of making self-aligned gate providing improved breakdown voltage
JPH06260507A (ja) * 1993-03-05 1994-09-16 Mitsubishi Electric Corp 半導体装置及びその製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4568631A (en) * 1984-04-30 1986-02-04 International Business Machines Corporation Process for delineating photoresist lines at pattern edges only using image reversal composition with diazoquinone

Also Published As

Publication number Publication date
EP0252888A3 (en) 1989-03-22
IT1203822B (it) 1989-02-23
EP0252888A2 (en) 1988-01-13

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