ITMI20041671A1 - "sistema e metodo e apparecchio per conservare un margine di errore per una memoria non volatile" - Google Patents

"sistema e metodo e apparecchio per conservare un margine di errore per una memoria non volatile"

Info

Publication number
ITMI20041671A1
ITMI20041671A1 IT001671A ITMI20041671A ITMI20041671A1 IT MI20041671 A1 ITMI20041671 A1 IT MI20041671A1 IT 001671 A IT001671 A IT 001671A IT MI20041671 A ITMI20041671 A IT MI20041671A IT MI20041671 A1 ITMI20041671 A1 IT MI20041671A1
Authority
IT
Italy
Prior art keywords
preserve
volatile memory
error margin
margin
error
Prior art date
Application number
IT001671A
Other languages
English (en)
Inventor
Lorenzo Bedarida
Massimiliano Frulio
Mirella Marsella
Caser Fabio Tassan
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to IT001671A priority Critical patent/ITMI20041671A1/it
Publication of ITMI20041671A1 publication Critical patent/ITMI20041671A1/it
Priority to US11/124,939 priority patent/US7269058B2/en
Priority to PCT/US2005/030143 priority patent/WO2006026309A2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/026—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/067—Single-ended amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/063—Current sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5645—Multilevel memory with current-mirror arrangements
IT001671A 2004-08-26 2004-08-26 "sistema e metodo e apparecchio per conservare un margine di errore per una memoria non volatile" ITMI20041671A1 (it)

Priority Applications (3)

Application Number Priority Date Filing Date Title
IT001671A ITMI20041671A1 (it) 2004-08-26 2004-08-26 "sistema e metodo e apparecchio per conservare un margine di errore per una memoria non volatile"
US11/124,939 US7269058B2 (en) 2004-08-26 2005-05-09 System and method for preserving an error margin for a non-volatile memory
PCT/US2005/030143 WO2006026309A2 (en) 2004-08-26 2005-08-23 System and method for preserving an error margin for a non-volatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT001671A ITMI20041671A1 (it) 2004-08-26 2004-08-26 "sistema e metodo e apparecchio per conservare un margine di errore per una memoria non volatile"

Publications (1)

Publication Number Publication Date
ITMI20041671A1 true ITMI20041671A1 (it) 2004-11-26

Family

ID=35942824

Family Applications (1)

Application Number Title Priority Date Filing Date
IT001671A ITMI20041671A1 (it) 2004-08-26 2004-08-26 "sistema e metodo e apparecchio per conservare un margine di errore per una memoria non volatile"

Country Status (2)

Country Link
US (1) US7269058B2 (it)
IT (1) ITMI20041671A1 (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7414891B2 (en) * 2007-01-04 2008-08-19 Atmel Corporation Erase verify method for NAND-type flash memories
US7882405B2 (en) * 2007-02-16 2011-02-01 Atmel Corporation Embedded architecture with serial interface for testing flash memories
JP2013117837A (ja) * 2011-12-02 2013-06-13 Toshiba Corp 半導体集積回路、および、半導体記憶装置
KR20130090642A (ko) 2012-02-06 2013-08-14 삼성전자주식회사 불휘발성 반도체 메모리 장치의 센스앰프 회로
KR20150116072A (ko) * 2014-04-04 2015-10-15 에스케이하이닉스 주식회사 전자 장치

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4524412A (en) 1983-06-06 1985-06-18 At&T Bell Laboratories Peak current controlled converter with additional current threshold control level to limit current tailout during overload conditions
US5157269A (en) 1991-01-31 1992-10-20 Unitrode Corporation Load current sharing circuit
EP0551530B1 (en) 1991-12-16 1997-12-29 Alcatel Amplifier biasing circuit suitable for a ring-trip detection system
US6373304B1 (en) 1997-10-02 2002-04-16 Robert J. Drost Techniques for making and using an improved loop filter which maintains a constant zero frequency to bandwidth ratio
DE10102443A1 (de) 2001-01-19 2002-08-01 Infineon Technologies Ag Stromquellenschaltung
US6717856B2 (en) * 2001-06-30 2004-04-06 Intel Corporation Method and apparatus for sen-ref equalization

Also Published As

Publication number Publication date
US20060044885A1 (en) 2006-03-02
US7269058B2 (en) 2007-09-11

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