ITMI20041927A1 - Sistema e metodo pee evitare l'offset e ridurre il footprint di una memoria non volatile - Google Patents

Sistema e metodo pee evitare l'offset e ridurre il footprint di una memoria non volatile

Info

Publication number
ITMI20041927A1
ITMI20041927A1 IT001927A ITMI20041927A ITMI20041927A1 IT MI20041927 A1 ITMI20041927 A1 IT MI20041927A1 IT 001927 A IT001927 A IT 001927A IT MI20041927 A ITMI20041927 A IT MI20041927A IT MI20041927 A1 ITMI20041927 A1 IT MI20041927A1
Authority
IT
Italy
Prior art keywords
pee
footprint
reduce
volatile memory
avoid offset
Prior art date
Application number
IT001927A
Other languages
English (en)
Inventor
Luca Figini
Massimiliano Frulio
Riccardo Riva
Andrea Sacco
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to IT001927A priority Critical patent/ITMI20041927A1/it
Publication of ITMI20041927A1 publication Critical patent/ITMI20041927A1/it
Priority to US11/126,473 priority patent/US7301814B2/en
Priority to PCT/US2005/035166 priority patent/WO2006044163A2/en
Priority to TW094134763A priority patent/TWI302316B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
IT001927A 2004-10-12 2004-10-12 Sistema e metodo pee evitare l'offset e ridurre il footprint di una memoria non volatile ITMI20041927A1 (it)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IT001927A ITMI20041927A1 (it) 2004-10-12 2004-10-12 Sistema e metodo pee evitare l'offset e ridurre il footprint di una memoria non volatile
US11/126,473 US7301814B2 (en) 2004-10-12 2005-05-11 System and method for avoiding offset in and reducing the footprint of a non-volatile memory
PCT/US2005/035166 WO2006044163A2 (en) 2004-10-12 2005-10-03 System and method for avoiding offset in and reducing the footprint of a non-volatile memory
TW094134763A TWI302316B (en) 2004-10-12 2005-10-05 System and method for avoiding offset in and reducing the footprint of a non-volatile memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT001927A ITMI20041927A1 (it) 2004-10-12 2004-10-12 Sistema e metodo pee evitare l'offset e ridurre il footprint di una memoria non volatile

Publications (1)

Publication Number Publication Date
ITMI20041927A1 true ITMI20041927A1 (it) 2005-01-12

Family

ID=36145060

Family Applications (1)

Application Number Title Priority Date Filing Date
IT001927A ITMI20041927A1 (it) 2004-10-12 2004-10-12 Sistema e metodo pee evitare l'offset e ridurre il footprint di una memoria non volatile

Country Status (3)

Country Link
US (1) US7301814B2 (it)
IT (1) ITMI20041927A1 (it)
TW (1) TWI302316B (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7583107B2 (en) * 2006-09-27 2009-09-01 Atmel Corporation Sense amplifier circuit for low voltage applications
US7882405B2 (en) * 2007-02-16 2011-02-01 Atmel Corporation Embedded architecture with serial interface for testing flash memories

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5333300A (en) 1991-02-11 1994-07-26 Intel Corporation Timing circuitry and method for controlling automated programming and erasing of a non-volatile semiconductor memory
US5355464A (en) 1991-02-11 1994-10-11 Intel Corporation Circuitry and method for suspending the automated erasure of a non-volatile semiconductor memory
US5828601A (en) * 1993-12-01 1998-10-27 Advanced Micro Devices, Inc. Programmed reference
US5539690A (en) * 1994-06-02 1996-07-23 Intel Corporation Write verify schemes for flash memory with multilevel cells
US5737748A (en) 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory
US5844839A (en) * 1995-07-19 1998-12-01 Texas Instruments Incorporated Programmable and convertible non-volatile memory array
US5717634A (en) 1995-07-19 1998-02-10 Texas Instruments Incorporated Programmable and convertible non-volatile memory array
US5638326A (en) * 1996-04-05 1997-06-10 Advanced Micro Devices, Inc. Parallel page buffer verify or read of cells on a word line using a signal from a reference cell in a flash memory device
US5732021A (en) 1996-07-19 1998-03-24 Smayling; Michael C. Programmable and convertible non-volatile memory array
US5717632A (en) * 1996-11-27 1998-02-10 Advanced Micro Devices, Inc. Apparatus and method for multiple-level storage in non-volatile memories
JPH11328967A (ja) * 1998-05-14 1999-11-30 Fujitsu Ltd 半導体記憶装置
US6044022A (en) * 1999-02-26 2000-03-28 Tower Semiconductor Ltd. Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays
US6262914B1 (en) 1999-08-11 2001-07-17 Texas Instruments Incorporated Flash memory segmentation
JP3420133B2 (ja) * 1999-10-13 2003-06-23 Ｎｅｃエレクトロニクス株式会社 半導体記憶装置
US6185128B1 (en) * 1999-10-19 2001-02-06 Advanced Micro Devices, Inc. Reference cell four-way switch for a simultaneous operation flash memory device
US6574141B2 (en) * 2000-12-29 2003-06-03 Intel Corporation Differential redundancy multiplexor for flash memory devices
US6459620B1 (en) * 2001-06-21 2002-10-01 Tower Semiconductor Ltd. Sense amplifier offset cancellation in non-volatile memory circuits by dedicated programmed reference non-volatile memory cells
US6438039B1 (en) * 2001-07-03 2002-08-20 Macronix International Co., Ltd. Erasing device and method for flash memory
US6725178B2 (en) 2002-01-15 2004-04-20 International Business Machines Corporation Use of hidden partitions in a storage device for storing BIOS extension files

Also Published As

Publication number Publication date
TWI302316B (en) 2008-10-21
US20060077709A1 (en) 2006-04-13
TW200617987A (en) 2006-06-01
US7301814B2 (en) 2007-11-27

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