ITMI922032A0 - Struttura di contatto tra due strati conduttori in un dispositivo a semiconduttore e procedimento per la fabbricazione di essa - Google Patents
Struttura di contatto tra due strati conduttori in un dispositivo a semiconduttore e procedimento per la fabbricazione di essaInfo
- Publication number
- ITMI922032A0 ITMI922032A0 IT92MI2032A ITMI922032A ITMI922032A0 IT MI922032 A0 ITMI922032 A0 IT MI922032A0 IT 92MI2032 A IT92MI2032 A IT 92MI2032A IT MI922032 A ITMI922032 A IT MI922032A IT MI922032 A0 ITMI922032 A0 IT MI922032A0
- Authority
- IT
- Italy
- Prior art keywords
- procedure
- manufacturing
- semiconductor device
- conductive layers
- contact structure
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
- H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
- H10D64/0113—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
- H10P32/1414—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
- H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
- H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
- H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/031—Manufacture or treatment of conductive parts of the interconnections
- H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
- H10W20/066—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying by forming silicides of refractory metals
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
- H10W20/44—Conductive materials thereof
- H10W20/4451—Semiconductor materials, e.g. polysilicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
- H10W20/48—Insulating materials thereof
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
- H10P14/6518—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer
- H10P14/6524—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being nitrogen
- H10P14/6526—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being nitrogen introduced into an oxide material, e.g. changing SiO to SiON
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
- H10P14/6536—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to radiation, e.g. visible light
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H10P14/6927—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22027691 | 1991-08-30 | ||
| JP4020204A JP2756886B2 (ja) | 1991-08-30 | 1992-02-05 | 半導体装置およびその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| ITMI922032A0 true ITMI922032A0 (it) | 1992-08-28 |
| ITMI922032A1 ITMI922032A1 (it) | 1994-02-28 |
| IT1256415B IT1256415B (it) | 1995-12-05 |
Family
ID=26357109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ITMI922032A IT1256415B (it) | 1991-08-30 | 1992-08-28 | Struttura di contatto tra due strati conduttori in un dispositivo a semiconduttore e procedimento per la fabbricazione di essa |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US5614745A (it) |
| JP (1) | JP2756886B2 (it) |
| KR (1) | KR960012573B1 (it) |
| DE (1) | DE4228679C2 (it) |
| IT (1) | IT1256415B (it) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3241106B2 (ja) * | 1992-07-17 | 2001-12-25 | 株式会社東芝 | ダイナミック型半導体記憶装置及びその製造方法 |
| JPH11238697A (ja) | 1998-02-23 | 1999-08-31 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
| US6090707A (en) | 1999-09-02 | 2000-07-18 | Micron Technology, Inc. | Method of forming a conductive silicide layer on a silicon comprising substrate and method of forming a conductive silicide contact |
| US6833556B2 (en) | 2002-08-12 | 2004-12-21 | Acorn Technologies, Inc. | Insulated gate field effect transistor having passivated schottky barriers to the channel |
| US7084423B2 (en) | 2002-08-12 | 2006-08-01 | Acorn Technologies, Inc. | Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
| DE10253164B3 (de) * | 2002-11-14 | 2004-06-17 | Infineon Technologies Ag | Speicherzellenfeld |
| DE102004063718B4 (de) * | 2004-12-31 | 2013-11-14 | Rehau Ag + Co. | Verfahren zur Herstellung von Verdrahtungskanälen und danach hergestellter Verdrahtungskanal |
| CN104170058B (zh) | 2011-11-23 | 2017-08-08 | 阿科恩科技公司 | 通过插入界面原子单层改进与iv族半导体的金属接触 |
| US9620611B1 (en) | 2016-06-17 | 2017-04-11 | Acorn Technology, Inc. | MIS contact structure with metal oxide conductor |
| WO2018094205A1 (en) | 2016-11-18 | 2018-05-24 | Acorn Technologies, Inc. | Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height |
| CN118969730B (zh) * | 2024-10-16 | 2025-03-04 | 物元半导体技术(青岛)有限公司 | 混合键合方法及混合键合结构 |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2164491B (en) * | 1984-09-14 | 1988-04-07 | Stc Plc | Semiconductor devices |
| JPS61285762A (ja) * | 1985-06-12 | 1986-12-16 | Toshiba Corp | 半導体装置およびその製造方法 |
| JPS62298168A (ja) * | 1986-06-18 | 1987-12-25 | Hitachi Ltd | 半導体装置 |
| JPS63182859A (ja) * | 1987-01-26 | 1988-07-28 | Hitachi Ltd | 半導体集積回路装置 |
| US5063423A (en) * | 1989-04-28 | 1991-11-05 | Nippondenso Co., Ltd. | Semiconductor memory device of a floating gate tunnel oxide type |
| US5017979A (en) * | 1989-04-28 | 1991-05-21 | Nippondenso Co., Ltd. | EEPROM semiconductor memory device |
| US5150179A (en) * | 1990-07-05 | 1992-09-22 | Texas Instruments Incorporated | Diffusionless source/drain conductor electrically-erasable, electrically-programmable read-only memory and method for making and using the same |
-
1992
- 1992-02-05 JP JP4020204A patent/JP2756886B2/ja not_active Expired - Fee Related
- 1992-08-28 DE DE4228679A patent/DE4228679C2/de not_active Expired - Fee Related
- 1992-08-28 IT ITMI922032A patent/IT1256415B/it active IP Right Grant
- 1992-08-29 KR KR1019920015675A patent/KR960012573B1/ko not_active Expired - Fee Related
-
1994
- 1994-12-12 US US08/355,332 patent/US5614745A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US5614745A (en) | 1997-03-25 |
| KR960012573B1 (ko) | 1996-09-23 |
| ITMI922032A1 (it) | 1994-02-28 |
| JP2756886B2 (ja) | 1998-05-25 |
| DE4228679C2 (de) | 1997-01-09 |
| KR930005203A (ko) | 1993-03-23 |
| IT1256415B (it) | 1995-12-05 |
| JPH05114579A (ja) | 1993-05-07 |
| DE4228679A1 (de) | 1993-03-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted | ||
| TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970829 |