ITRM20040418A1 - Modo di lettura a compressione di dati a piu' livelli per il collaudo di memorie. - Google Patents

Modo di lettura a compressione di dati a piu' livelli per il collaudo di memorie.

Info

Publication number
ITRM20040418A1
ITRM20040418A1 IT000418A ITRM20040418A ITRM20040418A1 IT RM20040418 A1 ITRM20040418 A1 IT RM20040418A1 IT 000418 A IT000418 A IT 000418A IT RM20040418 A ITRM20040418 A IT RM20040418A IT RM20040418 A1 ITRM20040418 A1 IT RM20040418A1
Authority
IT
Italy
Prior art keywords
data
reading method
multiple levels
testing memories
compression reading
Prior art date
Application number
IT000418A
Other languages
English (en)
Inventor
Giovanni Naso
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to IT000418A priority Critical patent/ITRM20040418A1/it
Publication of ITRM20040418A1 publication Critical patent/ITRM20040418A1/it
Priority to US11/127,810 priority patent/US7434152B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques
IT000418A 2004-08-25 2004-08-25 Modo di lettura a compressione di dati a piu' livelli per il collaudo di memorie. ITRM20040418A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT000418A ITRM20040418A1 (it) 2004-08-25 2004-08-25 Modo di lettura a compressione di dati a piu' livelli per il collaudo di memorie.
US11/127,810 US7434152B2 (en) 2004-08-25 2005-05-12 Multiple-level data compression read mode for memory testing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000418A ITRM20040418A1 (it) 2004-08-25 2004-08-25 Modo di lettura a compressione di dati a piu' livelli per il collaudo di memorie.

Publications (1)

Publication Number Publication Date
ITRM20040418A1 true ITRM20040418A1 (it) 2004-11-25

Family

ID=35942820

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000418A ITRM20040418A1 (it) 2004-08-25 2004-08-25 Modo di lettura a compressione di dati a piu' livelli per il collaudo di memorie.

Country Status (2)

Country Link
US (1) US7434152B2 (it)
IT (1) ITRM20040418A1 (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4317717B2 (ja) * 2003-01-22 2009-08-19 株式会社日立グローバルストレージテクノロジーズ 垂直記録用薄膜磁気ヘッドを用いた磁気ディスク装置
US7596729B2 (en) * 2006-06-30 2009-09-29 Micron Technology, Inc. Memory device testing system and method using compressed fail data
KR101208960B1 (ko) * 2010-11-26 2012-12-06 에스케이하이닉스 주식회사 반도체 장치 및 이의 테스트 방법
KR20150130608A (ko) 2014-05-13 2015-11-24 에스케이하이닉스 주식회사 메모리 장치
CN107391296B (zh) 2016-04-27 2020-11-06 慧荣科技股份有限公司 存取闪存模块的方法及相关的闪存控制器与记忆装置
US10019314B2 (en) 2016-04-27 2018-07-10 Silicon Motion Inc. Flash memory apparatus and storage management method for flash memory
CN111679787B (zh) 2016-04-27 2023-07-18 慧荣科技股份有限公司 闪存装置、闪存控制器及闪存存储管理方法
US10289487B2 (en) 2016-04-27 2019-05-14 Silicon Motion Inc. Method for accessing flash memory module and associated flash memory controller and memory device
CN107391026B (zh) * 2016-04-27 2020-06-02 慧荣科技股份有限公司 闪存装置及闪存存储管理方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3585378A (en) * 1969-06-30 1971-06-15 Ibm Error detection scheme for memories
US4872168A (en) * 1986-10-02 1989-10-03 American Telephone And Telegraph Company, At&T Bell Laboratories Integrated circuit with memory self-test
US5265055A (en) * 1988-10-07 1993-11-23 Hitachi, Ltd. Semiconductor memory having redundancy circuit
JPH05325598A (ja) 1992-05-22 1993-12-10 Texas Instr Japan Ltd 半導体記憶装置
EP0632468A1 (en) * 1993-06-30 1995-01-04 International Business Machines Corporation Fast data compression circuit for semiconductor memory chips including an abist structure
JPH0877797A (ja) 1994-09-01 1996-03-22 Fujitsu Ltd 半導体記憶装置
US5627786A (en) * 1995-02-10 1997-05-06 Micron Quantum Devices, Inc. Parallel processing redundancy scheme for faster access times and lower die area
US5535164A (en) * 1995-03-03 1996-07-09 International Business Machines Corporation BIST tester for multiple memories
US5563833A (en) * 1995-03-03 1996-10-08 International Business Machines Corporation Using one memory to supply addresses to an associated memory during testing
US5787097A (en) * 1996-07-22 1998-07-28 Micron Technology, Inc. Output data compression scheme for use in testing IC memories
US5966388A (en) * 1997-01-06 1999-10-12 Micron Technology, Inc. High-speed test system for a memory device
US5913928A (en) * 1997-05-09 1999-06-22 Micron Technology, Inc. Data compression test mode independent of redundancy
US6032274A (en) * 1997-06-20 2000-02-29 Micron Technology, Inc. Method and apparatus for compressed data testing of more than one memory array
US6072737A (en) * 1998-08-06 2000-06-06 Micron Technology, Inc. Method and apparatus for testing embedded DRAM
ITRM20010104A1 (it) * 2001-02-27 2002-08-27 Micron Technology Inc Modo di lettura a compressione di dati per il collaudo di memorie.

Also Published As

Publication number Publication date
US7434152B2 (en) 2008-10-07
US20060044880A1 (en) 2006-03-02

Similar Documents

Publication Publication Date Title
ITRM20010104A0 (it) Modo di lettura a compressione di dati per il collaudo di memorie.
ATE424685T1 (de) Schnittstelle für hohe datenrate
EP2047368A4 (en) NON-VOLATILE MEMORY SYSTEM AND DATA READING / WRITING METHOD FOR NON-VOLATILE MEMORY SYSTEM
DE602005010776D1 (de) EPC Datenverwalter
DE602004017147D1 (de) Währungsabgabeanordnung für einen automatisierten geldautomaten
FR2888975B1 (fr) Procede de securisation pour la protection de donnees
DE502005004657D1 (de) Redundantes datenbussystem
GB0407263D0 (en) Analysing image data
DE60314628D1 (de) Datenserver
FI20041096L (fi) Menetelmä tiedon lataamisen optimoimiseksi
TWI315474B (en) A memory interface device, method and system for accessing memory data
DE602004019880D1 (de) Bilderzeugungsvorrichtung, aufzeichnungsflüssigkeit, aufzeichnungsflüssigkeitskassette
SG114652A1 (en) Data reading apparatus
FI20030554L (fi) Järjestelmä porareikätiedon hallitsemiseksi
DE60232125D1 (de) Multi-Level Datenverarbeitung für die Aufzeichnung
DE602004017262D1 (de) Speicherkartenverbinder
IL182328A0 (en) Method for reading magnetic data
ITMO20030019A0 (it) Apparato e metodo di elettrostimolazione e relativo supporto dati.
EP1886226A4 (en) ASSOCIATIVE MEMORY AND SYSTEM AND METHOD FOR SEARCHING DATA
DE602004012987D1 (de) Datenspeichersystem
FI20030191A0 (fi) Menetelmä muistikortin osoittamiseksi, muistikorttia käyttävä järjestelmä, ja muistikortti
DE60333434D1 (de) Steuerungsgerät für Datenspeichereinrichtung
NL1027613A1 (nl) Geheugenmodule.
TWM266493U (en) Data access device for memory card
DE602007006896D1 (de) Datenaufzeichnungsverfahren