ITRM960563A0 - - Google Patents
Info
- Publication number
- ITRM960563A0 ITRM960563A0 ITRM960563A ITRM960563A ITRM960563A0 IT RM960563 A0 ITRM960563 A0 IT RM960563A0 IT RM960563 A ITRM960563 A IT RM960563A IT RM960563 A ITRM960563 A IT RM960563A IT RM960563 A0 ITRM960563 A0 IT RM960563A0
- Authority
- IT
- Italy
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/44—Indication or identification of errors, e.g. for repair
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/36—Data generation devices, e.g. data inverters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT96RM000563A IT1284245B1 (it) | 1996-08-05 | 1996-08-05 | Sistema di collaudo per moduli di memoria simm fabbricati con l'uso di chip di memoria affetti da difettosita' |
| SG1997002788A SG76524A1 (en) | 1996-08-05 | 1997-08-05 | Specialized hardware and software to test simm's manufactured using non compliant memory chips |
| EP97830413A EP0825615A3 (en) | 1996-08-05 | 1997-08-05 | System and method for testing audio RAM memories |
| KR1019970037319A KR19980018371A (ko) | 1996-08-05 | 1997-08-05 | 논 컴플리언트 메모리 칩을 이용하여 제조된 simm을 테스트하기 위한 특수 하드웨어 및 소프트웨어 |
| JP9243319A JPH10106294A (ja) | 1996-08-05 | 1997-08-05 | Simmメモリモジュールのための試験システムおよび方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT96RM000563A IT1284245B1 (it) | 1996-08-05 | 1996-08-05 | Sistema di collaudo per moduli di memoria simm fabbricati con l'uso di chip di memoria affetti da difettosita' |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| ITRM960563A0 true ITRM960563A0 (it) | 1996-08-05 |
| ITRM960563A1 ITRM960563A1 (it) | 1998-02-05 |
| IT1284245B1 IT1284245B1 (it) | 1998-05-14 |
Family
ID=11404384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT96RM000563A IT1284245B1 (it) | 1996-08-05 | 1996-08-05 | Sistema di collaudo per moduli di memoria simm fabbricati con l'uso di chip di memoria affetti da difettosita' |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP0825615A3 (it) |
| JP (1) | JPH10106294A (it) |
| KR (1) | KR19980018371A (it) |
| IT (1) | IT1284245B1 (it) |
| SG (1) | SG76524A1 (it) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100612127B1 (ko) | 2004-09-22 | 2006-08-11 | 삼성전자주식회사 | 메모리 모듈 테스트 방법 및 이를 위한 메모리 모듈의 허브 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5537631A (en) * | 1994-03-21 | 1996-07-16 | Current Logic Systems, Inc. | Memory management technique for defective memory |
-
1996
- 1996-08-05 IT IT96RM000563A patent/IT1284245B1/it active IP Right Grant
-
1997
- 1997-08-05 SG SG1997002788A patent/SG76524A1/en unknown
- 1997-08-05 EP EP97830413A patent/EP0825615A3/en not_active Withdrawn
- 1997-08-05 KR KR1019970037319A patent/KR19980018371A/ko not_active Withdrawn
- 1997-08-05 JP JP9243319A patent/JPH10106294A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP0825615A3 (en) | 1999-06-09 |
| SG76524A1 (en) | 2000-11-21 |
| JPH10106294A (ja) | 1998-04-24 |
| IT1284245B1 (it) | 1998-05-14 |
| KR19980018371A (ko) | 1998-06-05 |
| EP0825615A2 (en) | 1998-02-25 |
| ITRM960563A1 (it) | 1998-02-05 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted |