ITTO20030013A1 - Dispositivo dmos di dimensioni ridotte e relativo procedimento di fabbricazione. - Google Patents
Dispositivo dmos di dimensioni ridotte e relativo procedimento di fabbricazione.Info
- Publication number
- ITTO20030013A1 ITTO20030013A1 IT000013A ITTO20030013A ITTO20030013A1 IT TO20030013 A1 ITTO20030013 A1 IT TO20030013A1 IT 000013 A IT000013 A IT 000013A IT TO20030013 A ITTO20030013 A IT TO20030013A IT TO20030013 A1 ITTO20030013 A1 IT TO20030013A1
- Authority
- IT
- Italy
- Prior art keywords
- manufacturing procedure
- reduced dimension
- related manufacturing
- dmos device
- dmos
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/65—Lateral DMOS [LDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
- H10D30/0285—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs using formation of insulating sidewall spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
- H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
- H10D62/152—Source regions of DMOS transistors
- H10D62/153—Impurity concentrations or distributions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/257—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT000013A ITTO20030013A1 (it) | 2003-01-14 | 2003-01-14 | Dispositivo dmos di dimensioni ridotte e relativo procedimento di fabbricazione. |
| US10/758,699 US7205597B2 (en) | 2003-01-14 | 2004-01-14 | DMOS device of small dimensions and manufacturing process thereof |
| US11/716,078 US7521758B2 (en) | 2003-01-14 | 2007-03-08 | DMOS device of small dimensions and manufacturing process thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT000013A ITTO20030013A1 (it) | 2003-01-14 | 2003-01-14 | Dispositivo dmos di dimensioni ridotte e relativo procedimento di fabbricazione. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ITTO20030013A1 true ITTO20030013A1 (it) | 2004-07-15 |
Family
ID=33495875
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT000013A ITTO20030013A1 (it) | 2003-01-14 | 2003-01-14 | Dispositivo dmos di dimensioni ridotte e relativo procedimento di fabbricazione. |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US7205597B2 (it) |
| IT (1) | ITTO20030013A1 (it) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ITTO20030013A1 (it) * | 2003-01-14 | 2004-07-15 | St Microelectronics Srl | Dispositivo dmos di dimensioni ridotte e relativo procedimento di fabbricazione. |
| CN101180738B (zh) * | 2005-03-31 | 2012-05-02 | Nxp股份有限公司 | 不对称高电压器件和制造方法 |
| JP2010278312A (ja) * | 2009-05-29 | 2010-12-09 | Sanyo Electric Co Ltd | 半導体装置 |
| JP5700649B2 (ja) * | 2011-01-24 | 2015-04-15 | 旭化成エレクトロニクス株式会社 | 半導体装置の製造方法 |
| ITMI20121244A1 (it) * | 2012-07-17 | 2014-01-18 | St Microelectronics Srl | Transistore con contatti di terminale auto-allineati |
| DE102015003082B4 (de) * | 2015-03-11 | 2020-12-10 | Elmos Semiconductor Se | MOS Transistor mit einem verbesserten Einschaltwiderstand |
| US10840337B2 (en) | 2018-11-16 | 2020-11-17 | Atomera Incorporated | Method for making a FINFET having reduced contact resistance |
| US10840335B2 (en) | 2018-11-16 | 2020-11-17 | Atomera Incorporated | Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance |
| US10854717B2 (en) | 2018-11-16 | 2020-12-01 | Atomera Incorporated | Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance |
| US10847618B2 (en) * | 2018-11-16 | 2020-11-24 | Atomera Incorporated | Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance |
| US10818755B2 (en) | 2018-11-16 | 2020-10-27 | Atomera Incorporated | Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance |
| US10840336B2 (en) | 2018-11-16 | 2020-11-17 | Atomera Incorporated | Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5171705A (en) * | 1991-11-22 | 1992-12-15 | Supertex, Inc. | Self-aligned structure and process for DMOS transistor |
| JP3317347B2 (ja) * | 1999-09-02 | 2002-08-26 | 日本電気株式会社 | ダイオードを備えた半導体装置およびその製造方法 |
| ITTO20030013A1 (it) * | 2003-01-14 | 2004-07-15 | St Microelectronics Srl | Dispositivo dmos di dimensioni ridotte e relativo procedimento di fabbricazione. |
-
2003
- 2003-01-14 IT IT000013A patent/ITTO20030013A1/it unknown
-
2004
- 2004-01-14 US US10/758,699 patent/US7205597B2/en not_active Expired - Lifetime
-
2007
- 2007-03-08 US US11/716,078 patent/US7521758B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US7521758B2 (en) | 2009-04-21 |
| US7205597B2 (en) | 2007-04-17 |
| US20040251494A1 (en) | 2004-12-16 |
| US20070249124A1 (en) | 2007-10-25 |
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