ITTO20050056A1 - Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita' - Google Patents

Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita'

Info

Publication number
ITTO20050056A1
ITTO20050056A1 IT000056A ITTO20050056A ITTO20050056A1 IT TO20050056 A1 ITTO20050056 A1 IT TO20050056A1 IT 000056 A IT000056 A IT 000056A IT TO20050056 A ITTO20050056 A IT TO20050056A IT TO20050056 A1 ITTO20050056 A1 IT TO20050056A1
Authority
IT
Italy
Prior art keywords
segregation
impurities
manufacturing
increased capacity
soi slice
Prior art date
Application number
IT000056A
Other languages
English (en)
Inventor
Roberto Campedelli
Turi Luigi Di
Dino Faralli
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT000056A priority Critical patent/ITTO20050056A1/it
Priority to US11/347,801 priority patent/US20060194409A1/en
Publication of ITTO20050056A1 publication Critical patent/ITTO20050056A1/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00—Gettering within semiconductor bodies
    • H10P36/03—Gettering within semiconductor bodies within silicon bodies
    • H10P36/07—Gettering within semiconductor bodies within silicon bodies of silicon-on-insulator structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
IT000056A 2005-02-03 2005-02-03 Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita' ITTO20050056A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT000056A ITTO20050056A1 (it) 2005-02-03 2005-02-03 Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita'
US11/347,801 US20060194409A1 (en) 2005-02-03 2006-02-03 Process for manufacturing a SOI wafer with improved gettering capability

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000056A ITTO20050056A1 (it) 2005-02-03 2005-02-03 Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita'

Publications (1)

Publication Number Publication Date
ITTO20050056A1 true ITTO20050056A1 (it) 2006-08-04

Family

ID=36932450

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000056A ITTO20050056A1 (it) 2005-02-03 2005-02-03 Procedimento di fabbricazione di una fetta soi con aumentata capacita' di segregazione delle impurita'

Country Status (2)

Country Link
US (1) US20060194409A1 (it)
IT (1) ITTO20050056A1 (it)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130104728A (ko) * 2012-03-15 2013-09-25 에스케이하이닉스 주식회사 반도체 칩 및 이를 갖는 적층 반도체 패키지
US9231020B2 (en) 2014-01-16 2016-01-05 Tower Semiconductor Ltd. Device and method of gettering on silicon on insulator (SOI) substrate

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5106776A (en) * 1988-06-01 1992-04-21 Texas Instruments Incorporated Method of making high performance composed pillar dRAM cell
DE59409300D1 (de) * 1993-06-23 2000-05-31 Siemens Ag Verfahren zur Herstellung von einem Isolationsgraben in einem Substrat für Smart-Power-Technologien
US5478758A (en) * 1994-06-03 1995-12-26 At&T Corp. Method of making a getterer for multi-layer wafers
JPH09172061A (ja) * 1995-12-18 1997-06-30 Fuji Electric Co Ltd 半導体装置の製造方法
SE513471C2 (sv) * 1997-11-17 2000-09-18 Ericsson Telefon Ab L M Halvledarkomponent och tillverkningsförfarande för halvledarkomponent
US5929508A (en) * 1998-05-21 1999-07-27 Harris Corp Defect gettering by induced stress

Also Published As

Publication number Publication date
US20060194409A1 (en) 2006-08-31

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