ITTO20050630A1 - Dispositivo di potenza a semiconduttore a porta isolata formata in uno scavo e relativo procedimento di fabbricazione - Google Patents

Dispositivo di potenza a semiconduttore a porta isolata formata in uno scavo e relativo procedimento di fabbricazione

Info

Publication number
ITTO20050630A1
ITTO20050630A1 IT000630A ITTO20050630A ITTO20050630A1 IT TO20050630 A1 ITTO20050630 A1 IT TO20050630A1 IT 000630 A IT000630 A IT 000630A IT TO20050630 A ITTO20050630 A IT TO20050630A IT TO20050630 A1 ITTO20050630 A1 IT TO20050630A1
Authority
IT
Italy
Prior art keywords
excavation
power device
device formed
manufacturing procedure
semiconductor power
Prior art date
Application number
IT000630A
Other languages
English (en)
Inventor
Giuseppe Arena
Cateno Marco Camalleri
Stefania Fortuna
Angelo Magri
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT000630A priority Critical patent/ITTO20050630A1/it
Priority to US11/531,796 priority patent/US20070063272A1/en
Publication of ITTO20050630A1 publication Critical patent/ITTO20050630A1/it

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/64Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66Vertical DMOS [VDMOS] FETs
    • H10D30/668Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/111Field plates
    • H10D64/117Recessed field plates, e.g. trench field plates or buried field plates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0295Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the source electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107Buried supplementary regions, e.g. buried guard rings 
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149Source or drain regions of field-effect devices
    • H10D62/151Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156Drain regions of DMOS transistors
    • H10D62/157Impurity concentrations or distributions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/20Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311Gate electrodes for field-effect devices
    • H10D64/411Gate electrodes for field-effect devices for FETs
    • H10D64/511Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/683Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being parallel to the channel plane
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
IT000630A 2005-09-15 2005-09-15 Dispositivo di potenza a semiconduttore a porta isolata formata in uno scavo e relativo procedimento di fabbricazione ITTO20050630A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT000630A ITTO20050630A1 (it) 2005-09-15 2005-09-15 Dispositivo di potenza a semiconduttore a porta isolata formata in uno scavo e relativo procedimento di fabbricazione
US11/531,796 US20070063272A1 (en) 2005-09-15 2006-09-14 Semiconductor power device with insulated gate formed in a trench, and manufacturing process thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT000630A ITTO20050630A1 (it) 2005-09-15 2005-09-15 Dispositivo di potenza a semiconduttore a porta isolata formata in uno scavo e relativo procedimento di fabbricazione

Publications (1)

Publication Number Publication Date
ITTO20050630A1 true ITTO20050630A1 (it) 2007-03-16

Family

ID=37883216

Family Applications (1)

Application Number Title Priority Date Filing Date
IT000630A ITTO20050630A1 (it) 2005-09-15 2005-09-15 Dispositivo di potenza a semiconduttore a porta isolata formata in uno scavo e relativo procedimento di fabbricazione

Country Status (2)

Country Link
US (1) US20070063272A1 (it)
IT (1) ITTO20050630A1 (it)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI222685B (en) * 2003-12-18 2004-10-21 Episil Technologies Inc Metal oxide semiconductor device and fabricating method thereof
US7897462B2 (en) * 2008-11-14 2011-03-01 Semiconductor Components Industries, L.L.C. Method of manufacturing semiconductor component with gate and shield electrodes in trenches
US20100123193A1 (en) * 2008-11-14 2010-05-20 Burke Peter A Semiconductor component and method of manufacture
US8664713B2 (en) 2008-12-31 2014-03-04 Stmicroelectronics S.R.L. Integrated power device on a semiconductor substrate having an improved trench gate structure
IT1396561B1 (it) * 2009-03-13 2012-12-14 St Microelectronics Srl Metodo per realizzare un dispositivo di potenza con struttura trench-gate e relativo dispositivo
KR101107658B1 (ko) 2009-06-09 2012-01-20 주식회사 하이닉스반도체 반도체 소자의 제조방법
KR101142335B1 (ko) 2009-06-15 2012-05-17 에스케이하이닉스 주식회사 반도체 소자 및 그 제조방법
US8592266B2 (en) 2010-10-27 2013-11-26 International Business Machines Corporation Replacement gate MOSFET with a high performance gate electrode
US9006063B2 (en) * 2013-06-28 2015-04-14 Stmicroelectronics S.R.L. Trench MOSFET
CN106876276A (zh) * 2017-01-04 2017-06-20 上海华虹宏力半导体制造有限公司 沟槽型双层栅mos结构的制造方法
CN111863617A (zh) * 2019-04-24 2020-10-30 帅群微电子股份有限公司 沟槽式功率半导体组件及其制造方法
CN113437141A (zh) * 2021-06-24 2021-09-24 电子科技大学 一种具有多晶硅二极管栅极结构的浮空p区cstbt器件

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6147377A (en) * 1998-03-30 2000-11-14 Advanced Micro Devices, Inc. Fully recessed semiconductor device
US6156606A (en) * 1998-11-17 2000-12-05 Siemens Aktiengesellschaft Method of forming a trench capacitor using a rutile dielectric material
DE19935442C1 (de) * 1999-07-28 2000-12-21 Siemens Ag Verfahren zum Herstellen eines Trench-MOS-Leistungstransistors
JP4363736B2 (ja) * 2000-03-01 2009-11-11 新電元工業株式会社 トランジスタ及びその製造方法
GB0028031D0 (en) * 2000-11-17 2001-01-03 Koninkl Philips Electronics Nv Trench-gate field-effect transistors and their manufacture
TWI248136B (en) * 2002-03-19 2006-01-21 Infineon Technologies Ag Method for fabricating a transistor arrangement having trench transistor cells having a field electrode
US7091573B2 (en) * 2002-03-19 2006-08-15 Infineon Technologies Ag Power transistor
CN101421832A (zh) * 2004-03-01 2009-04-29 国际整流器公司 沟槽器件的自对准接触结构

Also Published As

Publication number Publication date
US20070063272A1 (en) 2007-03-22

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